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IDT Table of Contents
79RC32438 User Reference Manual
xii
November 4, 2002
Notes
Breakpoints Used as Triggerpoints................................................................................20-42
Instruction Breakpoint Registers....................................................................................20-43
Data Breakpoint Registers.............................................................................................20-47
Recommendations for Implementing Hardware Breakpoints.........................................20-51
Breakpoint Examples.....................................................................................................20-52
EJTAG Test Access Port..........................................................................................................20-54
TAP Signals....................................................................................................................20-55
TAP Controller................................................................................................................20-56
Instruction Register and Special Instructions.................................................................20-58
TAP Data Registers........................................................................................................20-59
Examples of Use............................................................................................................20-70
On-Chip Interfaces...................................................................................................................20-74
Optional JTAG_TRST_N Pin..........................................................................................20-74
Input Buffers with Pull-Up/Down and Output Drivers for Chip Pins................................20-74
Connecting Multi-Core Test Access Port (TAP) Controllers...........................................20-75
Off-Chip and Probe Interfaces.................................................................................................20-75
Logical Signals...............................................................................................................20-76
AC Timing Characteristics..............................................................................................20-77
DC Electrical Characteristics..........................................................................................20-79
Mechanical Connector ...................................................................................................20-80
Target System PCB Design............................................................................................20-81
Probe Requirements and Recommendations................................................................20-83
Appendix A 4Kc Processor Core
Instructions
Introduction................................................................................................................................. A-1
Understanding the Instruction Set.............................................................................................. A-1
Instruction Fields............................................................................................................... A-2
Instruction Descriptive Name and Mnemonic.................................................................... A-3
Format Field...................................................................................................................... A-3
Purpose Field.................................................................................................................... A-3
Description Field ............................................................................................................... A-3
Restrictions Field............................................................................................................... A-4
Operation Field.................................................................................................................. A-4
Exceptions Field................................................................................................................ A-5
Programming Notes and Implementation Notes Fields..................................................... A-5
Operation Section Notation and Functions................................................................................. A-5
Instruction Execution Ordering.......................................................................................... A-5
Special Symbols in Pseudocode Notation ........................................................................ A-6
Pseudocode Functions...................................................................................................... A-7
Op and Function Subfield Notation..................................................................................A-11
CPU Opcode Map......................................................................................................................A-11
Instruction Set........................................................................................................................... A-13
Index
.......................................................................................................................................................I-1