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IDT Table of Contents
79RC32438 User Reference Manual
ii
November 4, 2002
Notes
System Control Coprocessor...........................................................................................2-35
Exceptions.................................................................................................................................2-35
Exception Conditions .......................................................................................................2-35
Exception Priority.............................................................................................................2-35
Exception Vector Locations..............................................................................................2-36
General Exception Processing.........................................................................................2-38
Debug Exception Processing...........................................................................................2-39
Exceptions........................................................................................................................2-39
Exception Handling and Servicing Flowcharts.................................................................2-49
CP0 Registers............................................................................................................................2-54
CP0 Register Summary ...................................................................................................2-54
CP0 Registers..................................................................................................................2-56
Hardware and Software Initialization.........................................................................................2-79
Hardware Initialized Processor State...............................................................................2-79
Software Initialized Processor State ................................................................................2-80
Caches.......................................................................................................................................2-80
Cache Protocols...............................................................................................................2-81
Instruction Cache.............................................................................................................2-82
Data Cache......................................................................................................................2-82
Memory Coherence Issues..............................................................................................2-83
Power Management...................................................................................................................2-83
Register-Controlled Power Management.........................................................................2-83
Instruction-Controlled Power Management......................................................................2-83
Instruction Set............................................................................................................................2-84
Load and Store Instructions.............................................................................................2-84
Computational Instructions...............................................................................................2-85
Control Instructions..........................................................................................................2-86
Coprocessor Instructions .................................................................................................2-86
Enhancements to the MIPS Architecture.........................................................................2-86
Processor Core Instructions......................................................................................................2-87
3 Clocking and Initialization
Introduction..................................................................................................................................3-1
Block Diagram .............................................................................................................................3-1
Clocking Overview.......................................................................................................................3-1
Reset Register Description..........................................................................................................3-3
Reset and Initialization.................................................................................................................3-3
Cold Reset .........................................................................................................................3-3
Boot Configuration Vector..................................................................................................3-4
Reset/Initialization Registers.......................................................................................................3-6
Boot Configuration Vector Register....................................................................................3-6
Warm Reset .......................................................................................................................3-6
Reset Register ...................................................................................................................3-8
4 System Integrity Functions
Introduction..................................................................................................................................4-1
Features.......................................................................................................................................4-1
Functional Overview....................................................................................................................4-1