參數(shù)資料
型號(hào)： 8044
廠(chǎng)商： Intel Corp.
英文描述： CHMOS Single-Chip 8-Bit Microcontroller(CHMOS 單片、8位微控制器)
中文描述： CHMOS單片8位微控制器（CHMOS單片，8位微控制器）
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 616K
代理商： 8044
FLEXIBILITY IN FRAME SIZE WITH THE 8044
292019–9
Point-to-Point
Standard SDLC
Figure 7. Point-to-Point and Standard SDLC
Frame Formats
292019–10
Figure 8. Secondary Responses to Primary
Station Commands
system, one secondary is chosen to simplify the primary
station’s software and focus on the long frame software
code. Both the primary and the secondary stations are
in Flexible mode and the external clock option is used
for the serial channel. The maximum data rate is
500 Kbps. The FCS bytes are generated and checked
automatically by both stations.
6.1.1 POLLING SEQUENCE
The polling sequence, shown in Figure 8, takes place
continuously between the primary and the secondary
stations. The primary transmits a frame with one infor-
mation byte to the secondary. The information byte is
used by the secondary as an address byte. The second-
ary checks the received byte, and if the address
matches, the secondary responds with a long frame. In
this example, the information field of the frame is cho-
sen to be 255 bytes long. Since there is only one second-
ary station, the address always matches. Upon success-
ful reception of the long frame, the primary transmits
another frame to the secondary station.
6.1.2 HARDWARE
The schematic of the secondary station is given in Fig-
ure 9. The circuit of the primary station is identical to
the secondary station with the exception of pin 11
(DATA) being connected to pin 14 (T0). In the pri-
mary station, the 8044 is interrupted when activity is
detected on the communication line by the on-chip tim-
er (in counter mode). This is explained more later. The
serial clock to both stations is supplied by a pulse gen-
erator. The output of the pulse generator (not shown in
the diagram) is connected to pin 15 of the 8044s. Since
the two stations are located near each other (less than 4
feet), line drivers are not used.
The central processor of each station is the 8044. The
data link program is stored in a 2Kx8 EPROM
(2732A), and a 2Kx8 static RAM (AM9128) is used as
the external transmit and receive buffer. The RTS pin is
connected to the CTS pin. For simplicity, the stations
are assumed to be in the SDLC Normal Respond Mode
after Hardware reset.
6.1.3 PRIMARY STATION SOFTWARE
The assembly code for the primary station software is
listed in Appendix A. The primary software consists of
the main routine, the SIU interrupt routine, and the
receive interrupt routine. The receive interrupt routine
is executed when a long frame is being received.
In the flow charts that follow, all actions taken by the
SIU appear in squares, and actions taken by the on-chip
CPU appear in spheres.
10
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