參數(shù)資料
型號(hào)： 8044
廠商： Intel Corp.
英文描述： CHMOS Single-Chip 8-Bit Microcontroller(CHMOS 單片、8位微控制器)
中文描述： CHMOS單片8位微控制器（CHMOS單片，8位微控制器）
文件頁(yè)數(shù)： 8/36頁(yè)
文件大小： 616K
代理商： 8044
FLEXIBILITY IN FRAME SIZE WITH THE 8044
3.0 TRANSMIT AND RECEIVE
STATES
The simplified receive and transmit state diagrams are
shown in Figures 4 and 5, respectively. The numbers on
the left of each state represent the contents of the
SIUST register when the byte processor is in the stand-
by mode, and the instructions on the right of each state
represent the ‘‘state procedures’’ of that state. When the
byte processor executes these procedures the least three
significant bits of the SIUST register are being incre-
mented while the other bits remain unchanged. The
byte processor will jump from one state to another
without going into the standby mode when a condition-
al jump procedure executed by the byte processor is
true.
3.1 Receive State Sequence
When an opening flag (7EH) is detected by the bit
processor, the byte processor is triggered to execute the
procedures of the FLAG state. In the FLAG state, the
byte processor loads the contents of the RBS register
into the Special RAM (SRAR) register. SRAR is the
pointer to the internal RAM. The byte processor decre-
ments the contents of the Receive Buffer Length (RBL)
register and loads them into the DMA Count (DCNT)
register. The FCS GEN/CHK circuit is turned on to
monitor the serial data stream for Frame Check Se-
quence functions as per SDLC specifications.
Assuming there is an address field in the frame, con-
tents of the SIUST register will then be changed to
08H, causing the byte processor to jump to the AD-
DRESS state and wait (standby) for the next byte
boundary. As soon as the bit processor moves the ad-
dress byte into the SR shift register, a byte boundary is
achieved and the byte processor is triggered to execute
the procedures in the ADDRESS state.
In the ADDRESS state the received station address is
compared to the contents of the STAD register. If there
is no match, or the address is not the broadcast address
(FFH), reception will be aborted (SIUST
e
01H). Oth-
erwise, the byte processor jumps to the CONTROL
state (SIUST
e
10H) and goes into standby mode.
The byte processor jumps to the CONTROL state if
there exists a control field in the receiving frame. In
this state the control byte is moved to the RCB register
by the byte processor. Note that the only action taken
in this state is that a received byte, processed by the bit
processor, is moved to RCB. There is no other hard-
ware task performed, and DCNT and SRAR are not
affected in this state.
The next two states, PUSH-1 and PUSH-2, will be exe-
cuted if Frame check sequence (NFCS
e
0) option is
selected. In these two states the first and second bytes
of the information field are pushed into the 3-byte
FIFO (FIFO0, FIFO1, FIFO2) and the Receive Field
Length register (RFL) is set to zero. The 3-byte FIFO
is used as a pipeline to move received bytes into the
internal RAM. The FIFO prevents transfer of CRC
bytes and the closing flag to the receive buffer (i.e.,
when the ending flag is received, the contents of FIFO
are FLAG, FCS1, and FCS0.) The three byte FIFO is
collapsed to one byte in No FCS mode.
In the DMA-LOOP state the byte processor pushes a
byte from SR to FIFO0, moves the contents of FIFO2
to the internal RAM addressed by the contents of
SRAR, increments the SRAR and RFL registers, and
decrements the DCNT register. If more information
bytes are expected, the byte processor repeats this state
on the next byte boundaries until DMA Buffer End
occurs. The DMA Buffer End occurs if SRAR reaches
0BFH (192 decimal), DCNT reaches zero, or the RBP
bit of the STS register is set.
The BOV-LOOP state, the last state, is executed if
there is a buffer overrun. Buffer overrun occurs when
the number of information bytes received is larger than
the length of the receive buffer (RFL
l
RBL). This
state is executed until the closing flag is received.
At the end of reception, if the FCS option is used, the
closing flag and the FCS bytes will remain in the 3-byte
FIFO. The contents of the RCB register are used to
update the NSNR (Receive/Send Count) register. The
SIU updates the STS register and sets the serial inter-
rupt.
3.2 Transmit State Sequence
Setting the RTS bit puts the SIU in the transmit mode.
When the CTS pin goes active, the byte processor goes
into START-XMIT state. In this state the opening flag
is moved into the RAM Buffer (RB) register. The byte
processor jumps to the next state and goes into the
standby mode.
If the Pre-Frame Sync (PFS) option is selected, the
PFS1 and PFS2 states will be executed to transmit the
two Pre-Frame Sync bytes (00H or 55H). In these two
states the contents of the Pre-Frame Sync generator are
sent to the serial port while the Zero Insertion Circuit
(ZID) is turned off. ZID is turned back on automatical-
ly on the next byte boundary.
If the PFS option is not chosen, the byte processor
jumps to the FLAG state. In this state, the byte proces-
sor moves the contents of TBS into the SRAR register,
decrements TBL and moves the contents into the
DCNT register. The byte processor turns off the ZID
and turns on FCS GEN/CHK. The contents of FCS
GEN/CHK are not transmitted unless the NFCS bit is
4
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