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參數(shù)資料
| 型號(hào)： | 8044 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS Single-Chip 8-Bit Microcontroller(CHMOS 單片、8位微控制器) |
| 中文描述： | CHMOS單片8位微控制器（CHMOS單片，8位微控制器） |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 616K |
| 代理商： | 8044 |
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FLEXIBILITY IN FRAME SIZE WITH THE 8044
292019–4
Figure 4. Receive State Diagram
set. If a frame with the address field is chosen, it moves
the contents of the STAD register into the RB register
for transmission. At the same time, the opening flag is
being transmitted by the bit processor.
In the ADDRESS (SIUST
e
A0H) and CONTROL
(SIUST
e
A8H) states, TCB and the first information
byte are loaded into the RB register for transmission,
respectively. Note that in the CONTROL state, none of
the registers (e.g. DCNT, SRAR) are incremented, and
ZID and FCS GEN/CHK are not turned on or off.
The procedures in the DMA-LOOP state are similar to
the procedures of the DMA-LOOP in the receive state
diagram. The SRAR register pointer to the internal
RAM is incremented, and the DCNT register is decre-
mented. The contents of DCNT reach zero when all the
information bytes from the transmit buffer are trans-
mitted. A byte from RAM is moved to the RB register
for transmission. This state is executed on the following
byte boundaries until all the information bytes are
transmitted.
The FCS1 and the FCS2 states are executed to transmit
the Frame Check Sequence bytes generated by the FCS
generator, and the END-FLAG state is executed to
transmit the closing flag.
The XMIT-ACTION and the ABORT-ACTION
states are executed by the byte processor to synchronize
the SIU with the CPU clock. The XMIT-ACTION or
the ABORT-ACTION state is repeated until the byte
processor status is updated. At the end, the STS and the
TMOD registers are updated.
The two ABORT-SEQUENCE states (SIUST
e
E0H
and SIUST
e
E8H) are executed only if transmission
is aborted by the CPU (RTS or TBF bit of the STS
register is cleared) or by the serial data link (CTS signal
goes inactive or shut-off occurs in loop mode.)
5
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