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參數(shù)資料
| 型號： | 8044 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS Single-Chip 8-Bit Microcontroller(CHMOS 單片、8位微控制器) |
| 中文描述： | CHMOS單片8位微控制器（CHMOS單片，8位微控制器） |
| 文件頁數(shù)： | 5/36頁 |
| 文件大?。?/td> | 616K |
| 代理商： | 8044 |
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FLEXIBILITY IN FRAME SIZE WITH THE 8044
1.0 INTRODUCTION
The 8044 is a serial communication microcontroller
known as the RUPI (Remote Universal Peripheral In-
terface). It merges the popular 8051 8-bit microcontrol-
ler with an intelligent, high performance HDLC/SDLC
serial communication controller called the Serial Inter-
face Unit (SIU). The chip provides all features of the
microcontroller and supports the Synchronous Data
Link Control (SDLC) communications protocol.
There are two methods of operation relating to frame
size:
1) Normal operation (limited frame size)
2) Expanded operation (unlimited frame size)
In Normal operation the internal 192 byte RAM is
used as the receive and transmit buffer. In this opera-
tion, the chip supports data rates up to 2.4 Mbps exter-
nally clocked and 375 Kbps self-clocked. For frame
sizes greater than 192 bytes, Expanded operation is re-
quired. In Expanded operation the external RAM, in
conjunction with the internal RAM, is used as the
transmit and receive buffer. In this operation, the chip
supports data rates up to 500 Kbps externally clocked
and 375 Kbps self-clocked. In both cases, the SIU han-
dles many of the data link functions in hardware, and
the chip can be configured in either Auto or Flexible
mode.
The discussion that follows describes the operation of
the chip and the behavior of the serial interface unit.
Both Normal and Expanded operations will be further
explained with extra emphasis on Expanded operation
and its supporting software. Two examples of SDLC
communication systems will also be covered, where the
chip is used in Expanded operation. The discussion as-
sumes that the reader is familiar with the 8044 data
sheet and the SDLC communications protocol.
1.1 Normal Operation
In Normal operation the on-chip CPU and the SIU
operate in parallel. The SIU handles the serial commu-
nication task while the CPU processes the contents of
the on-chip transmit and receiver buffer, services inter-
rupt routines, or performs the local real time processing
tasks.
The 192 bytes of on-chip RAM serves as the interface
buffer between the CPU and the SIU, used by both as a
receive and transmit buffer. Some of the internal RAM
space is used as general purpose registers (e.g. R0–R7).
The remaining bytes may be divided into at least two
sections: one section for the transmit buffer and the
other section for the receive buffer. In some applica-
tions, the 192 byte internal RAM size imposes a limita-
tion on the size of the information field of each frame
and, consequently, achieves less than optimal informa-
tion throughput.
Figure 1 illustrates the flow of data when internal
RAM is used as the receive and transmit buffer. The
on-chip CPU allocates a receive buffer in the internal
RAM and enables the SIU. A receiving SDLC frame is
processed by the SIU and the information bytes of the
frame, if any, are stored in the internal RAM. Then,
the SIU informs the CPU of the received bytes (Serial
Channel interrupt). For transmission, the CPU loads
the transmitting bytes into the internal RAM and en-
ables the SIU. The SIU transmits the information bytes
in SDLC format.
292019–1
Figure 1. Transmission/Reception Data Flow Using Internal RAM
1
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