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參數(shù)資料
| 型號： | 8044 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS Single-Chip 8-Bit Microcontroller(CHMOS 單片、8位微控制器) |
| 中文描述： | CHMOS單片8位微控制器（CHMOS單片，8位微控制器） |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 616K |
| 代理商： | 8044 |
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FLEXIBILITY IN FRAME SIZE WITH THE 8044
Main Routine
First, the chip is initialized (see Figure 10). It is put in
Flexible mode, externally clocked, and ‘‘Flag-Informa-
tion Field-FCS-Flag’’ frame format. Pre-Frame Sync
option (PFS
e
1) and automatic Frame Check Se-
quence generation/detection (NFCS
e
0) are selected.
The on-chip transmit buffer starts at location 20H and
the transmit buffer length is set to 1. This one byte
buffer contains the address of the secondary station.
There is no on-chip receive buffer since the long frame
being received is moved to the external buffer. The
RTS, TBF, and RBE bits are set simultaneously. Set-
ting the RTS and TBF bits causes the SIU to transmit
the contents of the transmit buffer.
292019–12
Main Program
Figure 10. Primary Station Flow Charts
SIU Interrupt Routine
After transmission of the frame, the SIU interrupts the
on-chip CPU (SI is set). In the SIU interrupt service
routine, counter 0 is initialized and turned on (see Fig-
ure 11). The user program returns to perform other
tasks. After reception of the long frame, the SIU inter-
rupt routine is executed again. This time, RTS, TBF,
and RBE are set for another round of information ex-
change between the two stations.
SIU never interrupts while reception or transmission is
taking place. The SIU registers are updated and the SI
is set (serial interrupt) after the closing flag has been
received or transmitted. An SIU interrupt never occurs
if the receive interrupt routine or the transmit subrou-
tine is being executed.
Setting the RBE bit of the STS register puts the RUPI
in the receive mode. However, the jump to the receive
interrupt routine occurs only when a frame appears on
the serial port. Incoming frames can be detected using
the Pre-Frame Sync. option and one of the CPU timers
in counter mode. The counter external pin (T0) is con-
nected to the data line (pin 11 is tied to pin 14). Setting
the PFS (Pre-Frame Sync.) bit will guarantee 16 tran-
sitions before the opening flag of a flame.
292019–13
SIU Interrupt Routine
Figure 11. Primary Station Flow Charts
12
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