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參數(shù)資料
| 型號： | 8044 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS Single-Chip 8-Bit Microcontroller(CHMOS 單片、8位微控制器) |
| 中文描述： | CHMOS單片8位微控制器（CHMOS單片，8位微控制器） |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 616K |
| 代理商： | 8044 |
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FLEXIBILITY IN FRAME SIZE WITH THE 8044
ry is reached. Each time a byte boundary is detected in
the serial data stream, a burst of clock cycles (16 CPU
states) is generated for the byte processor to execute
one state of the state machine. When all the procedures
in the state are executed, a wait signal is asserted to
terminate the burst, and the byte processor waits for
the next byte boundary (standby mode). The lower the
data rate, the longer the byte processor will stay in the
standby mode.
2.2 Reception of Frames
Incoming data is NRZI decoded by the on-chip decod-
er. It is then passed through the zero insertion/deletion
(ZID) circuitry. The ZID not only performs zero inser-
tion/deletion, but also detects flags and Go Aheads
(GA) in the data stream. The data bits are then loaded
into the shift register (SR) which performs serial to par-
allel conversion. When 8 bits of data are collected in the
shift register, the bit processor triggers the byte proces-
sor to process the byte, and it proceeds to load the next
block of data into the shift register. The serial data is
also shifted, through SR, to a 16-bit register called
‘‘FCS GEN/CHK’’ for CRC checking. The byte proc-
essor takes the received address and control bytes from
the SR shift register and moves them to the appropriate
registers. If the contents of the shift register is expected
to be an information byte, the byte processor moves
them through a 3-byte FIFO to the internal RAM at a
starting location addressed by the contents of the Re-
ceive Buffer Start (RBS) register.
2.3 Transmission of Frames
In the transmit mode, the byte processor relinquishes a
byte to the bit processor by moving it to a register
called RB (RAM buffer). The bit processor converts
the data to serial form through the shift register, per-
forms zero bit insertion, NRZI encoding, and sends the
data to the serial port for transmission. Finally, the
contents of the FCS GEN/CHK and the closing flag
are routed to the serial port for transmission.
292019–3
Figure 3. SIU Block Diagram
3
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