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參數(shù)資料
| 型號： | 8044 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS Single-Chip 8-Bit Microcontroller(CHMOS 單片、8位微控制器) |
| 中文描述： | CHMOS單片8位微控制器（CHMOS單片，8位微控制器） |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 616K |
| 代理商： | 8044 |
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FLEXIBILITY IN FRAME SIZE WITH THE 8044
The counter registers are initialized such that the coun-
ter interrupt occurs before the opening flag of a frame.
When the PFS transitions appear on the data line, the
counter overflows and interrupts the CPU. The CPU
program jumps to the timer interrupt service routine
and executes the receive routine. In the receive routine,
the received frame is processed, and the information
bytes are moved to the external RAM. Note that the
maximum count rate of the 8051 counter is
(/24
of the
oscillator frequency. At 12 MHz, the data rate is limit-
ed to 500 Kbps.
Another method to detect a frame on the data line and
cause an interrupt is to use an external ‘‘Flag-Detect’’
circuit to interrupt the CPU. The ‘‘Flag Detect’’ circuit
can be an 8-bit shift register plus some TTL chips. If
this option is used, the RUPI must operate in externally
clocked mode because the clock is needed to shift the
incoming data into the shift register. With this option,
the maximum data rate is not limited by the maximum
count rate of the 8051 counter.
Receive Interrupt Routine
In Normal operation, the byte processor executes the
procedures of the FLAG state, jumps to the CON-
TROL state without going into the standby mode, and
executes 10–2 procedure of the state (see Figure 4). It
then jumps to the PUSH-1 state and goes into the
standby mode. At the following byte boundaries, the
byte processor executes the PUSH-1, PUSH-2, and
DMA-LOOP states, respectively. The receive interrupt
routine as shown in the flow chart of Figure 12 and
described below forces the byte processor to repeatedly
execute the CONTROL state before the PUSH-1 state
is executed. The following is the step by step procedure
to receive long frames:
1) Turn off the CPU counter and save all the impor-
tant registers. Jump to the receive interrupt routine,
execution of the instructions to save registers, and
initialization of the receive buffer pointer take place
while the Pre-Frame Sync bytes and the opening
flag are being received. This is about three data byte
periods (48 CPU cycles at 500 Kbps).
2) Monitor the SIUST register for standby in the
PUSH-1 state (SIUST
e
18H). When the SIUST
contents are 18H, the byte processor is waiting for
the first information byte. The bit processor has al-
ready recognized the flag and is processing the first
information byte.
3) In the standby mode, move the byte processor into
the CONTROL state by writing ‘‘EFH’’ (comple-
ment of 10H) into the SIUST register. When the
next byte boundary occurs, the bit processor has
processed and moved a byte of data into the SR
register. The byte processor moves the contents of
SR into the RCB register, jumps to the PUSH-1
state (SIUST
e
18H), and waits.
4) Monitor the SIUST register for standby in the
PUSH-1 state. When the contents of SIUST be-
comes 18H, the contents of RCB are the first infor-
mation byte of the information field.
5) While the byte processor is in the standby mode,
move the contents of RCB to an external RAM or
an I/O port.
6) Check for the end of the information field. The end
can be detected by knowing the number of bytes
transmitted, or by having a unique character at the
end of information field. The length of the informa-
tion field can be loaded into the first byte(s) re-
ceived. The receive routine can load this byte into
the loop counter.
7) If the byte received is not the last information byte,
move the byte processor back to standby in the
CONTROL state and repeat steps 4 through 6. Oth-
erwise, return from the interrupt routine.
Upon returning from the receive interrupt routine, the
byte processor automatically executes the PUSH-1,
PUSH-2, and DMA-LOOP before it stops. This causes
the remaining information bytes (if any) to be stored in
the internal RAM at the starting location specified by
the contents of RBS register. At the end of the cycle,
the closing flag and the CRC bytes are left in the FIFO.
The RFL register will be incremented by the number of
bytes stored in the internal RAM. Then, the STS and
NSNR registers are updated, and an appropriate re-
sponse is generated by the SIU.
The software to perform the above task is given in Ta-
ble 1. In this example, the number of instruction cycles
executed during standby is 12 cycles.
13
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