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參數(shù)資料
| 型號(hào)： | 8044 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS Single-Chip 8-Bit Microcontroller(CHMOS 單片、8位微控制器) |
| 中文描述： | CHMOS單片8位微控制器（CHMOS單片，8位微控制器） |
| 文件頁數(shù)： | 25/36頁 |
| 文件大小： | 616K |
| 代理商： | 8044 |
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FLEXIBILITY IN FRAME SIZE WITH THE 8044
292019–24
SIU Interrupt
Figure 22. Secondary Station Flow Charts
the RBE bit is set and the counter is turned on which
put the chip back in the receive mode.
6.2.5 RECEIVE INTERRUPT ROUTINE
Assembly code for the receive interrupt routine can be
found in both primary and secondary software (Appen-
dix B). The receive interrupt routine of the primary
station is very similar to that of the primary station in
example 1. In the following two sections the receive and
transmit routine of the secondary stations are dis-
cussed.
In the receive interrupt service routine (see Figure 23),
counter 0 is turned off, important registers are saved,
receive buffer starting address and receive buffer length
of the external RAM are set (do not confuse the exter-
nal RAM settings with that of the internal RAM buff-
er.)
After reception of an opening flag, the byte processor
jumps to the ADDRESS state and waits until the bit
processor processes and moves the receiving address
byte to SR. Then, the byte processor is triggered to
execute the state. In the secondary stations, the CPU
monitors the SIUST register for the ADDRESS state
(SIUST
e
08H). When the ADDRESS state is
reached, the byte processor is moved to the next state
(CONTROL state), and the ADDRESS state is
skipped. Therefore, when the address byte is moved to
SR, the byte processor executes the CONTROL state
rather than the ADDRESS state and then jumps to the
PUSH-1 state. The execution of the CONTROL state
causes the contents of SR (the received address byte) to
be loaded into the RCB register.
The CPU checks the contents of RCB with the contents
of the STAD (Station Address) register. If they match,
the receive routine continues to store the received In-
formation bytes in the external RAM buffer; Other-
wise, the byte processor is moved to the very last state
(BOV-LOOP), and the program returns from the rou-
tine to perform other tasks. The byte processor executes
the BOV-LOOP state in each byte boundary until the
closing flag of the frame is reached. It then sets the
BOV bit and interrupts the CPU (serial interrupt SI
set). In the serial interrupt routine the counter 0 is
turned back on, and the station is reset back to the
receive mode (RBE set).
In Normal operation, in the ADDRESS state, the re-
ceived address byte is automatically compared with the
station address. If they match, the byte processor exe-
cutes the remaining states; otherwise, the byte proces-
sor goes into the idle mode (SIUST
e
01H) and waits
for the opening flag of the next frame. In the expanded
operation, this state is skipped to avoid idle mode. If
the byte processor went into the idle mode, clocks
which run the byte processor would be turned off, and
the byte processor can not be moved to any other states
by the CPU. When the byte processor is in idle mode,
counter 0 can not be turned on immediately because
counter interrupt occurs on the same frame, and pro-
gram returns to the receive routine and stays there.
If the address byte matches the station address, the byte
processor is moved to the CONTROL state again. This
time, after execution of the CONTROL state the con-
tents of RCB are the received control byte.
CPU investigates the type of received frame by check-
ing the received control byte. If the receiving frame is
not an information frame (i.e. Supervisory frame), exe-
cution of receive routine will be terminated to free the
21
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