參數(shù)資料
型號： 82845PE
廠商： Intel Corp.
英文描述： 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述： 82845GE圖形和內(nèi)存控制器中樞（GMCH）和82845PE內(nèi)存控制器中樞（MCH）
文件頁數(shù)： 27/157頁
文件大?。?/td> 1407K
代理商： 82845PE
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
27
R
2.4.5.
AGP/PCI Signals-Semantics
For transactions on the AGP interface carried using AGP FRAME# protocol these signals operate similar
to their semantics in the PCI 2.1 specification the exact role of all AGP FRAME# signals are defined
below.
Table 11. AGP/PCI Signal Semantics Descriptions
Signal Name
Type
Description
G_FRAME#
I/O
s/t/s
AGP
G_FRAME:
Frame
During PIPE# and SBA Operation:
Not used by AGP SBA and PIPE# operations.
During Fast Write Operation:
Used to frame transactions as an output during
Fast Writes.
During FRAME# Operation:
G_FRAME# is an output when the MCH-M acts as
an initiator on the AGP Interface. G_FRAME# is asserted by the MCH-M to indicate
the beginning and duration of an access. G_FRAME# is an input when the MCH-M
acts as a FRAME#-based AGP target. As a FRAME#-based AGP target, the MCH-
M latches the C/BE[3:0]# and the AD[31:0] signals on the first clock edge on which
MCH-M samples FRAME# active.
G_IRDY#
I/O
s/t/s
AGP
G_IRDY#:
Initiator Ready
During PIPE# and SBA Operation:
Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.
During FRAME# Operation:
G_IRDY# is an output when MCH-M acts as a
FRAME#-based AGP initiator and an input when the MCH-M acts as a FRAME#-
based AGP target. The assertion of G_IRDY# indicates the current FRAME#-based
AGP bus initiator's ability to complete the current data phase of the transaction.
During Fast Write Operation:
In Fast Write mode, G_IRDY# indicates that the
AGP-compliant master is ready to provide all write data for the current transaction.
Once G_IRDY# is asserted for a write operation, the master is not allowed to insert
wait states. The master is never allowed to insert a wait state during the initial data
transfer (32 bytes) of a write transaction. However, it may insert wait states after
each 32-byte block is transferred.
G_TRDY#
I/O
s/t/s
AGP
G_TRDY#:
Target Ready
During PIPE# and SBA Operation:
Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.
During FRAME# Operation:
G_TRDY# is an input when the MCH-M acts as an
AGP initiator and is an output when the MCH-M acts as a FRAME#-based AGP
target. The assertion of G_TRDY# indicates the target’s ability to complete the
current data phase of the transaction.
During Fast Write Operation:
In Fast Write mode, G_TRDY# indicates the AGP-
compliant target is ready to receive write data for the entire transaction (when the
transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or
subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes.
The target is allowed to insert wait states after each block (32 bytes) is transferred
on write transactions.
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