參數(shù)資料
型號： 82845PE
廠商： Intel Corp.
英文描述： 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述： 82845GE圖形和內(nèi)存控制器中樞（GMCH）和82845PE內(nèi)存控制器中樞（MCH）
文件頁數(shù)： 83/157頁
文件大?。?/td> 1407K
代理商： 82845PE
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
83
R
3.7.37.
SMICMD – SMI Command Register – Device #0
Address Offset:
Default Value:
Access:
Size:
CC-CDh
0000h
Read/Write, Read Only
16 bits
This register enables various errors to generate an SMI message via the hub interface A.
Note:
An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SMI error message is enabled for an error condition; SERR and
SCI error messages are disabled for that same error condition.
Bit
Description
15:2
Reserved
1
SMI on Multiple-bit DRAM ECC Error (DMERR):
When this bit is set, the generation of the hub
interface A SMI message is enabled when the MCH-M DRAM controller detects a multiple-bit error.
For systems not supporting ECC this bit must be disabled.
0
SMI on Single-bit ECC Error (DSERR):
When this bit is set, the generation of the hub interface A
SMI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.
3.7.38.
SCICMD – SCI Command Register – Device #0
Address Offset:
Default Value:
Access:
Size:
CE-CDh
0000h
Read/Write, Read Only
16 bits
This register enables various errors to generate a SCI message via the hub interface A.
Note:
An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SCI error message is enabled for an error condition, SERR and
SMI error messages are disabled for that same error condition.
Bit
Description
15:2
Reserved
1
SCI on Multiple-Bit DRAM ECC Error (DMERR):
When this bit is set, the generation of the hub
interface A SCI message is enabled when the MCH-M DRAM controller detects a multiple-bit error.
For systems not supporting ECC this bit must be disabled.
0
SCI on Single-bit ECC Error (DSERR):
When this bit is set, the generation of the hub interface A
SCI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.
相關(guān)PDF資料
PDF描述
82845GE 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
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8284 TWO-OUTPUT LNB SUPPLY AND CONTROL-VOLTAGE REGULATOR
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