參數(shù)資料
型號: 82845PE
廠商: Intel Corp.
英文描述: 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述: 82845GE圖形和內(nèi)存控制器中樞(GMCH)和82845PE內(nèi)存控制器中樞(MCH)
文件頁數(shù): 68/157頁
文件大?。?/td> 1407K
代理商: 82845PE
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
68
Datasheet
250687-002
R
Extended System BIOS Area (E0000h-EFFFFh)
This 64-Kbytes area is divided into four 16-Kbytes segments which can be assigned with different
attributes via PAM control register as defined by the table above.
System BIOS Area (F0000h-FFFFFh)
This area is a single 64-Kbytes segment, which can be assigned with different attributes via PAM control
register as defined by the table above.
3.7.22.
FDHC – Fixed DRAM Hole Control Register – Device #0
Address Offset:
Default Value:
Access:
Size:
97h
Read/Write, Read Only
8 bits
This 8-bit register controls a fixed DRAM hole: 15 MB-16 MB.
Bit
Description
7
Hole Enable (HEN).
This field enables a memory hole in DRAM space. Host cycles matching an
enabled hole are passed on to ICH3-M through the hub interface. The hub interface cycles matching
an enabled hole will be ignored by the MCH-M. Note that a selected hole is not re-mapped.
0
1
Disabled. No hole
15 M-16 M (1 MB Hole)
6:0
Reserved
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