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參數(shù)資料
| 型號(hào)： | 82C836A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁(yè)數(shù)： | 160/205頁(yè) |
| 文件大?。?/td> | 3878K |
| 代理商： | 82C836A |
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Two PROCCLK cycles later, -REFRESH is asserted. For Master intitated refresh, the
add-on card bus master asserts -REFRESH. ALE follows HLDA and HOLD as in
DMA cycles.
-LOMEGCS follows -REFRESH.
Refresh address, -XMEMR and -RAS are synchronized to the 14.3MHz clock.
The width of -XMEMR is programmable (see ICR 41H). For AT-compatibility, the
width should be set to four clocks (280ns).
The width of -XMEMR can also be extended, one 14.3MHz clock cycle at a time, by
driving IOCHRDY low.
-MWE is the inverse of -CAS; it goes high while -CAS is low.
The delay from HLDA rise to -REF fall during CAS-before-RAS refresh allows for
CAS precharge time. The worst-case for CAS precharge is when a zero wait state
cache-mode write is immediately followed by a refresh cycle. CAS can extend past the
end of -READY by up to one full PROCCLK cycle in that case, as shown in Figure
11-16 (see also Figure 11-9).
When using nonencoded RAS, -RAS1 and -RAS2 are delayed slightly relative to
-RAS0 and -RAS3 during refresh. This staggered refresh is intended to reduce the
net instantaneous DRAM power surge resulting from -RAS assertion.
A0-10 contain the refresh address, incremented at the end of -REF (rising edge). A16-23
contain the Refresh Page register value, normally zero (programmable). A11-15 are
undefined. The DRAM uses its own internal refresh address counter during
CAS-before-RAS refresh, but the refresh address generated by the 82C836 is still needed
on the AT bus.
As in DMA cycles, HOLD is synchronized to PROCCLK. The falling edge always
occurs at the start of T-state.
When using RAS-only refresh instead of CAS-before-RAS refresh (see ICR 60H),
refresh timing differs from the foregoing as follows:
-CAS remains high during RAS-only refresh.
-MWE remains low during RAS-only refresh.
The two PROCCLK delay between -RAS rise and -REF fall is deleted; -REF goes low
on the same PROCCLK edge on which -RAS goes high.
The DRAMs rely on the 82C836 to provide the refresh address during RAS-only
refresh.
I
CPU Access to AT-Bus
System Timing Relationships
11-28
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C836A-16 | Single-Chip 386sx AT |
| 82C836A-20 | Single-Chip 386sx AT |
| 82C836B | Single-Chip 386sx AT |
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C836A-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C836A-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C836B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
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