Table 2-5.
I/O Channel Interface Signals (continued)
Pin
Type
Name
Description
41
Input
IOCHRDY
I/O Channel Ready is used by I/O channel or
XD-bus devices to lengthen their R/W cycles.
Normally, IOCHRDY is high; it is pulled low to
extend the cycle time. This input should be driven
by an open collector driver.
40
Input
-0WS (-LBA)
Zero Wait-State is an active-low input from the I/O
channel. This signal allows the present bus cycle to
terminate without inserting any additional wait-states
-0WS should be driven with an open collector or a
tri-state driver. For external cache support, this
signal can also be programmed to act as a Local Bus
Access (-LBA) input as well as the AT bus -0WS
input.
83
Bidirectional
-IOCS16
I/O 16-bit Chip Select is an active-low signal.
-IOCS16 is an input from the I/O channel and
XD-bus peripherals, indicating that the accessed
resource can support 16-bit data transfers. -IOCS16
is an output for I/O accesses to the EMS I/O ports.
-IOCS16 should be driven with an open collector or
tri-state driver.
82
Bidirectional
-MEMCS16
Memory 16-bit Chip Select is an active-low signal.
-MEMCS16 is an input from the I/O channel and
XD-bus peripherals, indicating that the accessed
resource can support 16-bit data transfers.
-MEMCS16 is an output for CPU or Master accesses
to on-board DRAM or to 16-bit on-board ROM.
42
Input
-IOCHCK
I/O Channel Check is an active-low signal from the
I/O channel used to trigger an NMI in the processor
in the event of an unrecoverable I/O channel error.
54-50
Input
IRQ0<3:7>
----
49
Input
IRQ09
----
84-86
Input
IRQ<10:12>
----
88-87
Input
IRQ<14:15>
Interrupt Requests 3-7, 9, 10-12, 14-15 are
asynchronous inputs to the 82C836 interrupt
controllers. These requests are prioritized with
IRQ03 having the highest priority and IRQ15 the
lowest. The request line is held active until
acknowledged by the processor with an interrupt
acknowledge cycle.
90
Input
DRQ0/DSELB
----
48
Input
DRQ1/DSELA
----
46
Input
DRQ2/DRQA
----
44
Input
DRQ3/DRQB
----
92
Input
DRQ5/-CAS3H
----
94
Input
DRQ6/-CAS2H
----
Pin Assignments
Signal Descriptions
I
Chips and Technologies, Inc.
P R E L I M I N A R Y
Revision 3.0
2-7