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參數(shù)資料
| 型號(hào)： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 12/96頁 |
| 文件大小： | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-12
MD400171/C
FUNCTIONAL DESCRIPTION
GENERAL
The 84302 is a quad Ethernet Controller for 100/10 Mbps
Ethernet systems. The 84302 ntegrates our ndependent
MAC (Media Access Control) sublayers, as defined in
IEEE 802.3. The 84302 has seven main sections: System
Interface, MAC, FIFO’s, PHY Interface, Management In-
terface, Register Interface, and Registers. Each of the
sections is replicated four times, once per port, with the
exception of the four interfaces (System, Register, PHY,
and Management), which are common to all four ports. A
top level block diagram is shown in Figure 1, and a block
diagram of each individual port is shown in Figure 2.
For each port, The 84302 has a transmit data path and a
receive data path. The transmit data path goes in the
System Interface and out the PHY Interface, as shown in
the top half of Figure 2. The receive data path goes in the
PHY Interface and out the System Interface, as shown in
the bottom half of Figure 2.
On the transmit data path, data for all four ports s nput nto
the System Interface from an external bus. One port has
to be selected, and the data is then sent to the transmit
FIFO of the selected port. The transmit FIFO provides
temporary storage of the data until it is sent to the transmit
MAC section for that port. The transmit MAC takes the
data and formats t nto an Ethernet packet per IEEE 802.3
specifications and shown n Figure 3. The Ethernet packet
then goes to the PHY Interface for formatting and trans-
mission to an external PHY chip. There are two PHY
Interface modes on the 84302: MII and 10 Mbps Serial.
The formatting of the data on the PHY Interface is done
according to IEEE 802.3 specifications and is also shown
in Figure 4. The transmit side manages collisions via the
internal backoff and defer algorithms and also generates
MAC Control Pause frames.
On the receive data path, the PHY Interface receives
incoming data from an external PHY chip for each port.
The incoming data must be in either MII or 10 Mbps Serial
format as specified in IEEE 802.3 and shown in Figure 4.
The PHY Interface converts the data from MII/10 Mbps
Serial ormat o Ethernet packet data. The Ethernet packet
data is then sent to the receive MAC section for that port.
The receive MAC section decomposes the packet, checks
the validity of the packet against certain error criteria and
address filters, and checks for MAC Control frames. The
receive MAC then sends valid packets to the receive FIFO
for that port. The receive FIFO provides temporary stor-
age of data until it is demanded by the System Interface.
The receive FIFO’s for all four ports can be individually
selected and accessed by the System Interface. The
System Interface outputs the data for the selected port to
an external bus.
The Register Interface is a separate bidirectional 16-bit
data bus hrough which configuration nputs can be set and
status outputs can be read from the internal registers and
management counters. The internal register bank is
replicated four times, once per port.
The Management Interface, referred to as the MI, is serial
interface for passing data to/from and external PHY.
Each block plus the operating modes are described in
more detail in the following sections.
ETHERNET FRAME FORMAT
General
Information in an Ethernet network is transmitted and
received in packets or frames. The basic function of the
84302 s to process Ethernet frames. An Ethernet frame s
defined in IEEE 802.3 and consists of a preamble, start of
frame delimiter (SFD), destination address (DA), source
address (SA) , length/type field (L/T), data, frame check
sequence (FCS), and interpacket gap (IPG). The format
for the Ethernet frame is shown in Figure 3.
An Ethernet frame is specified by IEEE 802.3 to have a
minimum ength of 64 bytes and a maximum ength of 1518
bytes, exclusive of the preamble and SFD. Packets which
are less than 64 bytes or greater than 1518 bytes are
referred to as undersize and oversize packets, respec-
tively.
Preamble & SFD
The preamble & SFD is a combined 64-bit field consisting
of 62 alternating 1’s and 0’s followed by a 11 end of
preamble indicator. The first 56-bits of 1’s and 0’s are
considered to be the preamble, and the last 8-bits of
10101011 are considered to be the SFD (Start of Frame
Delimiter).
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