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參數(shù)資料
| 型號： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 21/96頁 |
| 文件大小： | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-21
MD400171/C
controlled by other bits described in the MAC Control
Frame section
Table 4. Multicast Address Filter Map
FCS Bits
[0:2]
Address
Filter Byte
FCS Bits
[3:5]
Address
Filter Bit
000
F0[7:0]
000
Fx[0]
001
F1[7:0]
001
Fx[1]
010
F2[7:0]
010
Fx[2]
011
F3[7:0]
011
Fx[3]
100
F4[7:0]
100
Fx[4]
101
F5[7:0]
101
Fx[5]
110
F6[7:0]
110
Fx[6]
111
F7[7:0]
111
Fx[7]
F[7:0] are bytes in Hash Filter 0-7 Registers.
Fx[7:0] are bits within each byte in Hash Filter 0-7 Registers.
Bits 0-5 are the six least signficant bits of the CRC.
Broadcast Address Filter
The device does not do any filtering on broadcast packets.
However, the device can be programmed to accept or
reject broadcast packets, regardless of their address, by
appropriately setting the receive address match select bits
in the RX Command register.
The reception of MAC Control frames s unaffected by any
of the broadcast packet address filtering functions and is
controlled by other bits described in the MAC Control
Frame section
Reject Or Accept All Packets
The device can be programmed to accept or reject all
packets regardless of type or whether the packet passes
the address filter by appropriately setting the receive
address match select bits in the RX Command register.
The reception of MAC Control frames is unaffected by
these bits and is controlled by other bits described in the
MAC Control Frame section.
Frame Validity Checks
The receive MAC determines the validity of each receive
packet by checking for (1) valid FCS, (2) oversize packet,
and (3) undersize packet.
Valid FCS is determined by computing the CRC value on
the ncoming receive packet per EEE 802.3 specifications
and comparing it against the actual CRC value present in
the FCS field of the received packet. If the values are not
the same, (1) the frame s determined to be nvalid and the
packet s discarded, f he discard eature s enabled (2) he
CRC error detect bit s set n the RX Status register, (3) the
CRC error bit s set n he receive status word or he packet
and (4) he nterrupt pin or he port s asserted provided he
interrupt function is enabled. Refer to the Packet Discard
section for more information about discards. The device
can be programmed to
not
discard and accept all receive
packets with bad FCS by setting the CRC error accept bit
in the RX Command register.
Oversize packets are packets whose ength s greater han
the maximum packet size. If a received packet is an
oversize packet, then (1) the packet is determined to be
invalid and it is discarded if the discard feature is enabled,
(2) the oversize packet detect bit is set in the RX Status
register, and (3) the interrupt pin for the port is asserted
provided the interrupt function is enabled. Refer to the
Packet Discard section for more information about dis-
cards. The maximum packet size can be programmed to
be any one of sixteen values between 1518 bytes and
1533 bytes, exclusive of preamble & SFD, by appropriately
setting he maximum packet size select bits n he Configu-
ration 5 register. The device also can be programmed to
not
discard and accept all receive oversize packets,
regardless of size, by setting he oversize packet accept bit
in the RX Command register.
Undersize packets are packets whose length is less than
the minimum packet size. Minimum packet size s defined
to be 64 bytes, exclusive of preamble & SFD. If a received
packet is an undersize packet, then (1) the frame is
determined to be invalid and it is discarded if the discard
feature s enabled, (2) he undersize packet detect bit s set
in the RX Status register, and (3) the interrupt pin for the
port is asserted provided the interrupt function is enabled.
Refer to the Packet Discard section for more information
about discards. The device can also be programmed to
not
discard and accept all receive undersize packets by
setting the undersize packet accept bit in the RX Com-
mand register.
If a receive packet contains dribble bits, that s, the receive
packet contains a non-integer number of bytes, the condi-
tion s ndicated by setting the dribble error detect bit n the
RX Status register.
RX Status Register
Each port contains one RX Status register which stores he
status of the last packet received. With each reception
attempt, whether the packet s discarded or not, the status
register s written with the status for that packet. When the
RX Status register is written, the receive status update bit
is set in that register to indicate that the register contains
new information. The data remains latched in the RX
Status register until t s read out via the Register Interface.
Thus, no new receive status for a packet can be written
until the register is read. When the RX Status register is
read, he receive status update bit s cleared ow o ndicate
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