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參數(shù)資料
| 型號： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 38/96頁 |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-38
MD400171/C
When the bus width is set to 8-bits wide (BUSSIZE=0), all
registers have a unique address as determined by the
A[7:0] pins, as shown in Table 15. To read out the 32-bit
counter result over the 8-bit Register Interface bus, four
successive reads on the same address will have to be
done to output all 4 bytes of the 32-bit result. The first 8-
bit word that is read out contains the upper 8-bits of the
counter result (MS byte), and the fourth 8-bit contains the
lowest 8-bits (LS byte). Note that when the bus width s set
to 8-bit wide, the byte enables inputs on BE[3:0] are
ignored.
When the bus width is set to 16-bits wide (BUSSIZE=1),
the address pin A0 is ignored, and all registers have a
unique address determined by A[7:1], as shown in Table
15. To read out the 32-bit counter result over the 16-bit
Register Interface bus, two successive reads on the same
address will have to be done to output all 2 double words
of the 32-bit result. The first 16-bit word that is read out
contains the upper 16-bits of the counter result (MS word),
and the last 16-bit contains the lower 16-bits (LS word).
Note that when the bus width is set to 16-bit wide, the A0
address input is ignored.
The Byte Enable pins, BE[1:0], control which byte of the
16-bit word is accessed when the Register Interface is
configured for 16-bit bus width. The Byte Enable pins are
ignored when the Register Interface is configured to be 8-
bits.
Bit Types
The Register Interface s bidirectional, and there are many
types of bits in the registers. Write bits (W) are inputs
during a write cycle and are logic 0 during a read cycle.
Read bits (R) are outputs during a read cycle and are high
impedance and ignored during a write cycle. Read/Write
bits (R/W) are actually write bits which can be read out
during a read cycle. R/LH bits are read bits that latch
themselves when they go high, and they stay latched high
until read. After they are read, they are cleared ow. R/LHI
bits are the same as R/LH bits except that they also assert
REGISTER INTERFACE
General
The Register Interface s a selectable 8/16-bit bidirectional
data interface that allows access to the internal registers.
Timing
The Register Interface consists of thirty seven signals:
sixteen bidirectional data I/O pins (CDST[15:0]), eight
register address inputs (A[7:0]), one chip select input
(ENREGIO), one read select input (RD), one write select
input (WR), two port select inputs (REGPS[1:0], one bus
size select input (BUSSIZE), two byte enable inputs
(BE[1:0]), one data ready output (READY), and four inter-
rupt outputs, one per port (INT_[1:4]).
To access a register through the Register Interface,
ENREGIO must first be asserted active low. Then either
RD or WR needs to be asserted active low, and which
signal is asserted will determine whether this is a read or
write cycle. On that same falling edge of either RD or WR,
the address of the register that will be accessed needs to
be present on A[7:0], and the port to be selected must be
present on REGPS[1:0]. If the cycle is a write cycle (WR
asserted), then the data on CDST[15:0] will be written to
the designated register. If the cycle is a read cycle (RD
asserted), then data from the designated register will be
output on CDST[15:0] after some delay after the falling
edge of RD. The READY output will then go active high to
indicate that the data on CDST[15:0] is valid. READY will
stay high as ong as RD s asserted, and return ow after RD
is deasserted. READY is placed in high impedance state
when ENREGIO is deasserted and driven when
ENREGIO is asserted. ENREGIO can remain low for
multiple read or write cycles so that many registers can be
read or written to in one ENREGIO assertion.
Bus Width
The bus width of the Register Interface can be selected to
be either 8 or 16-bits wide by appropriately setting the
BUSSIZE pin.
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