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參數(shù)資料
| 型號： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 18/96頁 |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-18
MD400171/C
802.3. The device can be programmed to AutoPad by
setting the AutoPad enable bit in the Configuration 1
register.
CRC Generation
The ransmit MAC computes he CRC value on he packet,
and it normally appends this CRC value to the end of the
data packet from the transmit FIFO. The device can be
programmed to
not
append the CRC value to the end of
the packet by asserting he TXNOCRC pin or by setting he
transmit CRC disable bit in the Configuration 1 register.
The ogic nteraction between he TXNOCRC pin and CRC
disable bit is described in Table 3.
Table 3. TXCRC Bit & TXNOCRC Pin Logic
TXCRC_DIS
Bit
1=No Append
0=Append
TXNOCRC
Pin
1=No Append
0=Append
CRC
Appended to
End of Packet
1
1
No
1
0
No
0
1
No
0
0
Yes
Interpacket Gap
The interval between packets is called the interpacket
gap, also referred to as IPG. The minimum IPG is
controlled by the defer mechanism. The defer mechanism
is an internal algorithm which computes a defer time. If
packets from the transmit FIFO arrive at the transmit MAC
sooner than the defer time, the defer mechanism will add
enough IPG time between packets to equal the defer time
value.
In Half Duplex mode, the defer time is defined as the time
from the falling edge of CRS to the next rising edge of
TXEN (CRS is normally asserted during half duplex mode
transmission due to PHY loopback behavior). In Full
Duplex mode, he defer ime s defined as he ime rom he
falling edge of TXEN to the next rising edge of TXEN.
blocked and no data can be loaded into it until it is cleared
with CLRRXERR and the start of a new packet s detected.
See the Packet Discard section for more details on dis-
cards and RXDC_[1:4].
The RXABORT input, when asserted, will discard the
contents of the receive FIFO, and halt the reception of any
more data into the receive FIFO until the start of the next
packet s detected. Refer to the Packet Discard section for
more information about discarded packets. The device
can be programmed to disable and ignore the RXABORT
pin by setting the RXABORT pin disable bit n the Configu-
ration 2 register.
A status word can be appended to the end of the receive
packet, if desired. Refer to the Receive Status Word
section for more details on the status word. The status
word s always output on the next full 32-bit word boundary
after the data packet has ended, as shown in Figure 4.
TRANSMIT MAC
General
The transmit MAC (Media Access Control) section re-
ceives data from the transmit FIFO and generates an
Ethernet MAC frame from this transmit FIFO data by (1)
generating preamble & SFD, (2) padding undersize packet
with 0’s to meet minimum packet size requirements, (3)
calculating and appending CRC value, and (4) maintain-
ing the required minimum interpacket gap to meet the
defer requirements. In addition, the transmit MAC will also
retransmit data in the event of a collision. Each of the
above operations can be individually disabled and modi-
fied, if desired. The transmit MAC then sends the fully
formed Ethernet packet to the PHY Interface for transmis-
sion. The transmit MAC section also generates MAC
Control frames. The status of the last two packets trans-
mitted is available in the TX Status register.
Preamble & SFD Generation
The transmit MAC normally appends the preamble and
SFD to the packet. The device can be programmed to
not
append the preamble & SFD to the transmit packet by
setting the transmit preamble disable bit in the Configura-
tion 1 register.
AutoPad
AutoPadding is the process of automatically adding
enough zeroes on packets with data fields less than 46
bytes to make the data field exactly 46 bytes in length and
meet the 46 byte minimum data field requirement of IEEE
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