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參數(shù)資料
| 型號： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 14/96頁 |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-14
MD400171/C
Byte Order
The byte ordering of the RXTXDATA data bits is program-
mable by appropriately setting the endian select bit in the
Configuration 2 register. The byte order shown in Figure
4 is the little endian format (default). If big endian format
is selected, then the byte order shown in Figure 4 is
reversed, that is, DA[0:7] occurs on pins
RXTXDATA[24:31], DA[24:31] occurs on pins
RXTXDATAD[0:7], etc. This difference between little
endian and big endian format is illustrated in Figure 5.
Note that the byte order of the Status word appended to
Receive Packets s not affected by Big/Little Endian Selec-
tion
Transmit Write Operation
All receive and transmit data is clocked in/out on rising
edges of the system clock, SCLK. The SCLK input needs
to be continuously input to the device at a frequency
between 25-50 MHz.
The System Interface is bidirectional. When it is config-
ured for a transmit write operation, data is input into the
device and stored in the transmit FIFO. A transmit write
operation is initiated by asserting TXINTEN and
TXWREN. TXINTEN acts as a general transmit enable
input, and asserting TXINTEN also activates the output
drivers for the TXRDY and TXRET pins and removes them
from high impedance state. Coincident or after TXINTEN
is asserted, TXWREN has to be asserted to actually start
the write operation. If TXWREN is then asserted while
TXINTEN is asserted, the data word on the
RXTXDATA[31:0] I/O pins is clocked into the transmit
FIFO on each rising edge of the SCLK clock for the port
selected by the RXTXPS[1:0] inputs. TXINTEN and
TXWREN can be continuously asserted and deasserted
as many times as desired while a packet is being written
into the device. The last word of the packet must be
indicated to the device by asserting RXTXEOF on the
same SCLK rising edge that clocks in the last word of the
packet. TXWREN does not need to be deasserted be-
tween the end of one packet and the start of the next.
RXTXDATA[31:0] input data is 32-bit wide packet data
whose ormat and relationship o he MAC packet and PHY
Interface is described in Figure 4.
The byte enable pins, RXTXBE[3:0], are used for both
transmit and receive operation, and they determine which
bytes of the 32-bit RXTXDATA[31:0] data word contain
valid data. RXTXBE[3:0] are inputs during a ransmit write
operation, and are clocked in on rising edges of SCLK
along with each RXTXDATA[31:0] data word. The corre-
spondence between the byte enable inputs and the valid
bytes of each data word on RXTXDATA[31:0] s defined n
Table 2. Any logic combination of RXTXBE[3:0] inputs is
allowed, with the one exception that RXTXBE[3:0] must
not be 1111.
Data
The data is a 46-1500 byte field containing the actual data
to be transmitted between two stations. If the actual data
is less than 46 bytes, extra 0’s are added to increase the
data field to the 46 byte minimum. Adding these extra 0’s
is referred to as padding.
Frame Check Sequence
The frame check sequence (FCS), s a 32-bit cyclic redun-
dancy check (CRC) value computed on the entire frame,
exclusive of preamble & SFD. The FCS algorithm is
defined in IEEE 802.3. The FCS is appended to the end
of the frame and is used to determine frame validity.
Interpacket Gap
The interpacket gap (IPG) is the time interval between
packets. The minimum IPG value is defined to be 96 bits,
where 1 bit=10ns for 100 Mbps Ethernet & 1 bit=100nS for
10 Mbps Ethernet. There is no maximum IPG limit.
SYSTEM INTERFACE
General
The System Interface s a 32-bit wide bidirectional parallel
data interface. Data to/from any of the four independent
ports is input and output through the System Interface.
The System Interface consists of 64 signals: 32 bidirec-
tional data I/O (RXTXDATA[31:0]), four bidirectional byte
enable I/O (RXTXBE[3:0]), one receive and one transmit
enable input (RXINTEN and TXINTEN), one receive read
enable and one transmit write enable nput (RXRDEN and
TXWREN), two port select inputs (RXTXPS[1:0]), one
bidirectional end of frame I/O (RXTXEOF), one transmit
and one receive FIFO watermark output (RXRDY and
TXRDY), one transmit and one receive discard output
(RXDC and TXRET), one receive and one ransmit discard
clear input (CLR_RXERR and CLRTXERR), one transmit
CRC enable input (TXNOCRC), four flow control inputs
(FCNTRL_[1:4], one per port), one FIFO space/data avail-
able output (SPDTAVL), four receive FIFO overflow indi-
cation outputs (RXOVF_[1:4], one per port), and four
receive FIFO abort nputs (RXABORT_[1:4], one per port).
All data is clocked in/out on rising edges of the system
clock, SCLK. SCLK can operate between 25-50 MHZ.
Data Format and Bit Order
The format of the data word on RXTXDATA[31:0] and its
relationship to the MAC frame format and PHY Interface
format is shown in Figure 4. Note that the device can be
programmed to append an additional 32-bit status word to
the end of the receive packet; refer to the Receive Status
Word section for more details on this status word.
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