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參數(shù)資料
| 型號： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 27/96頁 |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-27
MD400171/C
SQE
SQE (short for Signal Quality Error) s a pulse outputted on
the COL pin by an external PHY after the reception of each
receive packet. SQE is only enabled in 10 Mbps Serial
mode. The detection of SQE pulses by the 84302 is
reported on the SQE detect bit n the Miscellaneous Status
register.
MANAGEMENT INTERFACE (MI)
General
The Management Interface, referred to as the MI, is a
serial interface for passing data between an internal reg-
ister and an external PHY. The MI meets all IEEE 802.3
Clause 22 requirements.
The MI consists of two signals: one MI clock output (MDC),
and one bidirectional data line (MDIO).
Data Format and Bit Order
The format of a MI data transfer cycle is defined in IEEE
802.3 Clause 22 and shown in Figure 6. The definition of
each bit transmitted over the MI is defined in Table 8. An
MI data transfer cycle consists of 64 bits: (1) The first 32
bits are the idle pattern, (2) the next 16 bits are always
written from the device to an external PHY and contain
command nformation related to the MI data transfer cycle,
and (3) the last 16 bits contain the actual data transferred
over the MI. These last sixteen bits are output from the
device when a write cycle is selected; they are input to the
device when a read cycle is selected.
Bit Definition
The bits comprising a MI data transfer cycle are defined in
Table 8. Some of the bits in a MI data transfer cycle are
read from/written to specific register bits. Other MI data
transfer cycle bits are generated by internal logic. The
source of each MI data transfer bit is defined in Table 8.
Note that the registers are replicated per port; thus, the
values used on any particular MI data transfer cycle are
obtained from the MI registers of the selected port.
Write Operation
A write operation is defined to be an MI data transfer cycle
where he ast 16 bits of data n he rame are obtained rom
the MI Data 0-1 Registers and are output onto the MDIO
pin and written to the external PHY. A write operation is
selected by appropriately setting he read/write select bit n
the MI Command/Status 1 register. After this bit is written,
then a write MI data transfer cycle is initiated on the MDC
and MDIO pins. After he write MI cycle has completed and
all the data is successfully written out, the MI status bit in
the MI Command/Status 1 register s set o ndicate hat he
operation is complete. The interrupt pin will be asserted
after a write operation has completed if the interrupt bit is
set in the MI Command/Status 1 register. After the
completion of a write operation, he MDC clock s urned off
and MDIO is held high.
Read Operation
A read operation is defined to be an MI data transfer cycle
where the ast 16 bits of data n the frame are read from an
external PHY and latched into the device from the MDIO
pin and internally stored in the MI Data 0-1 Registers. A
read operation is selected by appropriately setting the
read/write select bit in the MI Command/Status 1 register.
After this bit is written, then a read MI data transfer cycle
is initiated on the MDC and MDIO pins. After a read MI
cycle has completed and all he data s successfully oaded
into the MI Data registers, the MI status bit in the MI
Command/Status 1 register is set to indicate that the
operation is complete. The interrupt pin will be asserted
after a read operation has completed if the interrupt bit is
set in the MI Command/Status 1 register. After the
completion of a read operation, the MDC clock s turned off
and MDIO is held high.
Figure 6. MI Frame Format and Bit Order
MDC
MDIO
MDIO
(READ)
0
1
31
0
1
2
3
4
5
8
9
10
13
14
15
16
17
30
31
1
1
1
0
1
0
1
P4
P3
P0
R4
R3
R0
1
0
D15
D14
D1
D0
1
1
0
1
1
0
P4
P3
P0
R4
R3
R0
0
D15
D14
D1
D0
1
D[15:0]
TA[1:0]
REGAD[4:0]
PHYAD[4:0]
OP[1:0]
ST[1:0]
IDLE[31:0]
.......
.......
.......
.......
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