參數(shù)資料
型號(hào): 84302
廠商: LSI Corporation
英文描述: 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
中文描述: 4端口快速以太網(wǎng)控制器(4端口快速以太網(wǎng)控制器)
文件頁(yè)數(shù): 25/96頁(yè)
文件大?。?/td> 826K
代理商: 84302
84302 4-Port
Fast Ethernet Controller
4-25
MD400171/C
Table 7. Receive Status Word Definition
RXTXDATA31
RXTXDATA16
BC15
BC14
BC13
BC12
BC11
BC10
BC9
BC8
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RXER
RXAB
GOOD OSIZE
USIZE
DRIB
CRC
OVFL
RXTXDATA15
RXTXDATA0
Symbol
Name
Definition
Position On
RXTXDATA[31:0]
Pins
BC[15:0]
Byte Count
Contains Actual Byte Count of Receive Packet
RXTXDATA[31:16]
Reserved
RXTXDATA[15:9]
RXER
RXER Error
1 = Receive Packet had RXER symbol error reported
over MII from external PHY
RXTXDATA8
RXAB
Packet
RXABORT
1 = Receive Packet was aborted with RXABORT pin
RXTXDATA7
Reserved
RXTXDATA6
GOOD
Good Packet
1 = Receive Packet is a Good Frame
RXTXDATA5
OSIZE
Oversize Error
1 = Receive Packet is Greater Than Minimum Size
RXTXDATA4
USIZE
Undersize Error
1 = Receive Packet is Less Than Minimum Size
RXTXDATA3
DRIB
Dribble Error
1 = Receive Packet has a Non-Integer # of
Bits or Nibbles (Dribble)
RXTXDATA2
CRC
CRC Error
1 = Receive Packet has a CRC Error
RXTXDATA1
OVFL
RX FIFO
Overflow Error
1 = Receive FIFO is Full and more Data is Attempting to be
Inputted
RXTXDATA0
RECEIVE STATUS WORD
General
A 32-bit status word can be appended to the end of each
receive data packet and stored in the receive FIFO. This
status word contains a byte count and error nformation for
the receive data packet.
Format and Bit Order
The format for the status word s shown n Table 7. The top
16-bits contain he actual byte count or he packet, and he
bottom 16-bits contain the status nformation related to the
packet.
The byte count value n the status word s the total number
of bytes stored in the RX FIFO for the particular packet.
The byte count always includes the 4 bytes associated
with the CRC, independent of whether the CRC has been
removed or not by the receive MAC. The byte count also
does not include the preamble octets.
The Receive Status Word s always read out of the system
interface on the next full 32-bit word boundary, following
the end of packet data, as shown in Figure 4.
Status Word Disable
The status word is normally appended to the end of all
good receive packets. The receive status word can be not
appended to the end of the packet and thus disabled by
setting the status word disable bit in the Configuration 3
register.
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