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參數(shù)資料
| 型號： | 84302 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（4端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 17/96頁 |
| 文件大?。?/td> | 826K |
| 代理商： | 84302 |
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84302 4-Port
Fast Ethernet Controller
4-17
MD400171/C
to be continuously input to the device at a frequency
between 25-50 MHz.
The System Interface is bidirectional. When it is config-
ured for a receive read operation, data that s stored n the
receive FIFO is output to the System Interface. A receive
read operation is initiated by asserting RXINTEN and
RXRDEN. RXINTEN acts as a general receive enable
input, and asserting RXINTEN also activates the output
drivers for the RXRDY and RXDC pins and removes them
from high impedance state. Coincident or after RXINTEN
is asserted, RXRDEN has to be asserted to actually start
the read operation. If RXRDEN is then asserted while
RXINTEN is asserted, the oldest data word in the receive
FIFO s clocked out onto the RXTXDATA[31:0] I/O pins on
each rising edge of the SCLK clock for the port selected by
the RXTXPS[1:0] inputs. RXINTEN and RXRDEN can be
continuously asserted and deasserted as many times as
desired while a packet s being written nto the device. The
last word of the packet is indicated by the assertion of
RXTXEOF on the same SCLK rising edge that clocks out
the last word of the packet. Once the entire packet has
been clocked out, then no more data is clocked out on
RXTXDATA[31:0] for 8 SCLK cycles, thus allowing extra
dribble SCLK clock cycles to occur after the end of packet,
up to a maximum of 8 SCLK’s. After 8 extra dribble SCLKs
without a RXRDEN deassertion, the next packet will be
read out of the receive FIFO. If there is no packet in FIFO
after 8 extra dribble SCLKs, then invalid data will be read
out. RXTXDATA[31:0] input data is 32- bit wide packet
data whose ormat and relationship o he MAC packet and
PHY Interface is described in Figure 4.
The byte enable pins, RXTXBE[3:0], are used for both
transmit and receive operation, and they determine which
bytes of the 32-bit RXTXDATA[31:0] data word contain
valid data. RXTXBE[3:0] can be configured to be either
inputs or outputs during a receive read operation by
appropriately setting the byte enable direction bit in the
Configuration 3 register. When they are configured as
outputs, RXTXBE[3:0] are clocked out on rising edges of
SCLK along with each data word and ndicate which bytes
of the 32-bit RXTXDATA[31:0] data word contain valid
data. Note that RXTXBE[3:0]=0000 for all words of the
packet except the last word; the last word of the packet
may end on any one of the four byte boundaries of the 32-
bit data word. When they are configured as inputs,
RXTXBE[3:0] are clocked in on rising edges of SCLK
along with each RXTXDATA[31:0] data word and indicate
to the device which bytes contain the actual data. The
correspondence between the byte enable inputs and the
valid bytes of each data word on RXTXDATA[31:0] is
defined n Table 2. Any ogic combination of RXTXBE[3:0]
inputs s allowed, with he one exception hat RXTXBE[3:0]
must not be 1111.
The end of frame I/O pin, RXTXEOF, ndicates which data
word is the last word of the Ethernet data packet.
RXTXEOF is configured to be an output during a receive
read operation, and s output on the rising edges of SCLK.
The position of RXTXEOF during System Interface read
operations can be programmed to occur either (1) when
the receive status word s read out, or (2) when both he ast
data word of packet and the receive status word are read
out. This selection of either a single RXTXEOF at status
word or a double RXTXEOF at end of data and status word
is accomplished by appropriately setting the receive EOF
position select bit in the Configuration 2 register. The
selection of the EOF position s also affected by the setting
of the status word disable bit in Configuration 3 register.
The EOF position as a function of both the EOF position bit
and status word disable bit is shown in Table 2a. More
details about the status word can be found in the Receive
Status Word section.
Table 2a. RXTXEOF Position
SWRD_DIS
(Bit 2, Cfg Reg.2)
0
0
0
1
1
0
1
1
RXTXEOF Position
Status Word
Data
Data & Status Word
Data
There are four receive FIFO ready outputs, one per port,
on the RXRDY_[1:4] pins. The receive FIFO ready output
is a receive FIFO watermark signal which indicates when
the receive FIFO data has exceeded the programmable
receive FIFO threshold value. RXRDY_[1:4] will be
asserted or deasserted by the device on rising edges of
SCLK, depending on the fullness of the receive FIFO.
Refer to the receive FIFO section for more details on
RXRDY_[1:4].
In addition to the RXRDY output, there is also a FIFO
space/data available output indication on the SPDTAVL
pin. During a read operation, the SPDTAVL output is a
data available (almost empty) indication for the receive
FIFO and it is asserted active high if there is more than 1
double words of data present in the receive FIFO.
RXDC_[1:4] is a receive packet discard output, one per
port. RXDC_[1:4] s asserted when an error was detected
for a receive packet. When a receive error is detected on
a packet, the remaining contents of the RX FIFO are
flushed and RXDC_[1:4] is latched active high to indicate
the error condition. RXDC_[1:4] for the selected port can
be cleared by asserting the clearing signal, CLRRXERR.
While RXDC_[1:4] is latched high, the RX FIFO input is
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