參數(shù)資料
型號: 845GL
廠商: Intel Corp.
英文描述: Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
中文描述: 英特爾82845G/82845GL/82845GV圖形和內存控制器中樞(GMCH)
文件頁數(shù): 23/193頁
文件大?。?/td> 2990K
代理商: 845GL
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁
Intel
82845G/82845GL/82845GV GMCH Datasheet
23
Signal Description
2.1
Host Interface Signals
Signal Name
Type
Description
ADS#
I/O
AGTL+
Address Strobe:
The processor bus owner asserts ADS# to indicate the first of
two cycles of a request phase.
BNR#
I/O
AGTL+
Block Next Request:
This signal is used to block the current request bus
owner from issuing a new requests. This signal is used to dynamically control
the processor bus pipeline depth.
BPRI#
O
AGTL+
Priority Agent Bus Request:
The GMCH is the only Priority Agent on the
processor bus. It asserts this signal to obtain the ownership of the address bus.
This signal has priority over symmetric bus requests and will cause the current
symmetric owner to stop issuing new transactions unless the HLOCK# signal
was asserted.
BREQ0#
O
AGTL+
Bus Request 0#:
The GMCH pulls the processor bus’ BREQ0# signal low
during CPURST#. The signal is sampled by the processor on the active-to-
inactive transition of CPURST#. The minimum setup time for this signal is
4HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20
HCLKs. BREQ0# is terminated high (pulled up) after the hold time requirement
has been satisfied.
CPURST#
O
AGTL+
CPU Reset:
The CPURST# pin is an output from the GMCH. The GMCH
asserts CPURST# while RSTIN# (PCIRST# from Intel
ICH4) is asserted and
for approximately 1 ms after RSTIN# is deasserted. The CPURST# allows the
processors to begin execution in a known state.
DBSY#
I/O
AGTL+
Data Bus Busy:
This signal is used by the data bus owner to hold the data bus
for transfers requiring more than one cycle.
DEFER#
O
AGTL+
Defer:
This signal, when asserted, indicates that the GMCH will terminate the
transaction currently being snooped with either a deferred response or with a
retry response.
DINV_[3:0]#
I/O
AGTL+
4X
Dynamic Bus Inversion:
These signals are driven along with the HD_[63:0]#
signals. They indicates if the associated signals are inverted or not.
DINV_[3:0]# are asserted such that the number of data bits driven electrically
low (low voltage) within the corresponding 16-bit group never exceeds 8.
DINV
_
[x]#
Data Bits
DINV_3#
HD_[63:48]#
DINV_2#
HD_[47:32]#
DINV_1#
HD_[31:16]#
DINV_0#
HD_[15:0]#
DRDY#
I/O
AGTL+
Data Ready:
DRDY# is asserted for each cycle that data is transferred.
HA_[31:3]#
I/O
AGTL+
2X
Host Address Bus:
HA_[31:3]# connect to the processor address bus. During
processor cycles, HA_[31:3]# are inputs. The GMCH drives HA_[31:3]# during
snoop cycles on behalf of the hub interface and AGP/Secondary PCI initiators.
HA_[31:3]# are transferred at 2X rate. Note that the address is inverted on the
processor bus.
HADSTB_[1:0]#
I/O
AGTL+
2X
Host Address Strobe:
HADSTB_[1:0]# are the source synchronous strobes
used to transfer HA[31:3]# and HREQ_[4:0]# at the 2X transfer rate.
Strobe
Address Bits
HADSTB_0#
A[16:3]#, REQ[_4:0]#
HADSTB_1#
A[31:17]#
HD_[63:0]#
I/O
AGTL+
4X
Host Data:
These signals are connected to the processor data bus. Data on
HD_[63:0]# is transferred at a 4X rate. Note that the data signals may be
inverted on the processor bus.
相關PDF資料
PDF描述
845GV Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
8460 LAN 10/100 Base-TX Dual Port Transformer Modules
8461 LAN 10/100 Base-TX Dual Port Transformer Modules
8462 LAN 10/100 Base-TX Dual Port Transformer Modules
8463 LAN 10/100 Base-TX Dual Port Transformer Modules
相關代理商/技術參數(shù)
參數(shù)描述
845GLMS-L 制造商:Micro-Star International 功能描述:845GL UATX P4/CEL 400FSB - Bulk
845GR 制造商:SPC 功能描述:New
845-GR 制造商:SPC Technology 功能描述:INSULATED BANANA JACK 制造商:VOLTREK 功能描述:INSULATED BANANA JACK
845GV 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
845GVM-L 制造商:Micro-Star International 功能描述:845GV UATX P4/CEL 533FSB - Bulk