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參數(shù)資料
| 型號： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 220K |
| 代理商： | A8259 |
66
Altera Corporation
a8259 Programmable Interrupt Controller Data Sheet
OCW 1
OCW 1 is selected by setting the
a0
pin high. Input data for OCW 1 is sent
via the
din[7..0]
bus, and the data is clocked by the rising edge of
clk
.
Table 8
describes the OCW 1 register format.
OCW 2
OCW 2 is selected by setting the
a0
pin and resetting bits 3 and 4 of the
din[7..0]
bus low. Input data for OCW 2 is sent via the
din[7..0]
bus, and the data is clocked by the rising edge of
clk
.
Table 9
describes the OCW 2 register format.
Table 8. OCW 1 Register Format
Bit
Mnemonic
Description
1
2
3
4
5
6
7
M0
M1
M2
M3
M4
M5
M6
M7
When more than one of these bits is high, the
corresponding interrupt request inputs are masked;
otherwise, they are not masked.
Table 9. OCW 2 Register Format
Bit
Mnemonic
Description
0
1
2
3
4
5
6
7
L0
L1
L2
1
1
EOI
SL
R
Interrupt level. These bits determine the interrupt level
that is acted upon when bit 6 (SL) is asserted (see
Table 10
).
These bits are used as address decode and must
always be low.
These bits control the rotate and end of interrupt (EOI)
commands (see
Table 11
on
page 67
).
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