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參數(shù)資料
| 型號： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 220K |
| 代理商： | A8259 |
72
Altera Corporation
a8259 Programmable Interrupt Controller Data Sheet
Figure 6
shows the timing waveforms for the 3-byte interrupt sequence
mode.
Figure 6. 3-Byte Interrupt Sequence Mode Timng Waveforms
X indicates “Dont Care.”
Single-Byte Interrupt Sequence Mode
The single-byte interrupt sequence mode provides an 8-bit interrupt
vector. The interrupt sequence for this mode is as follows:
1.
One or more of the
ir[7..0]
signals are high, which sets the
corresponding bit in the IRR.
2.
The
a8259
checks the priority and masks for the interrupt, and if
appropriate, sets the
int
signal.
3.
The microprocessor responds by asserting
ninta
to the
a8259
.
4.
The
a8259
latches the
ir
signal on the falling edge of the
ninta
signal (when level-triggered). The
a8259
sets the corresponding ISR
bit on the following rising edge of the
ninta
signal. Simultaneously,
the interrupt request bit is reset, and no data is driven onto the
dout[7..0]
bus for this cycle.
5.
The microprocessor issues a second
ninta
pulse. An 8-bit interrupt
vector is driven onto the
dout[7..0]
bus. See
Table 20
.
clk
Level-triggered
interrupt request
or
int
ninta
Edge-triggered
interrupt request
Level-triggered interrupt
request is clocked by the
falling edge of ninta.
X
X
dout[7..0]
Call Code
1st Vector
Data
2nd Vector
Data
X
X
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