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參數(shù)資料
| 型號： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 220K |
| 代理商： | A8259 |
Altera Corporation
75
a8259 Programmable Interrupt Controller Data Sheet
Special Mask Mode
In SMM, masking an interrupt does not inhibit the reception of lower
priority interrupts. Only the interrupt being serviced is masked. With
SMM, any interrupt may be selectively enabled using the mask register.
Trigger Modes
Interrupt request lines may be configured in an edge- or level-triggered
mode. In edge-triggered mode, an interrupt request is clocked on the
rising edge of the clock. In level-triggered mode, an interrupt is generated
merely by placing a high on an
ir
pin. This level must be maintained until
after the falling edge of the first
ninta
pulse of the interrupt sequence.
The trigger mode can be programmed in bit 3 of the ICW 1 command
register.
Poll Command
The poll command provides a way to expand a system allowing the
microprocessor to service more than 64 interrupts. In poll mode, the
int
signal should be ignored. Each
a8259
is “polled” individually to
determine which interrupts are requesting service. After setting the poll
(using bit 2 of OCW 3), the microprocessor simply reads from each
a8259
(each interrupt read transaction must be preceded by a write transaction
to the poll bit in order to reset the ISR). If an interrupt is pending, the
corresponding ISR bit is set on the falling edge of the read cycle, and an
interrupt ID byte (bit 7) set high is placed on the
dout[7..0]
bus.
Table 21
shows the interrupt ID word format for the poll command.
Table 21. Interrupt ID Word Format
Bit
Decode
Description
0
1
2
3
4
5
6
7
ID0
ID1
ID2
Don’t Care
Don’t Care
Don’t Care
Don’t Care
IP
Interrupt ID. These bits identify the pending
interrupt.
–
–
–
–
Interrupt pending. When set, this bit indicates an
interrupt is pending. If this bit is cleared, the
interrupt ID will be ignored.
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