參數(shù)資料
型號(hào)： a8259
廠商： Altera Corporation
英文描述： Programmable Interrupt Controller(可編程中斷控制器)
中文描述： 可編程中斷控制器（可編程中斷控制器）
文件頁(yè)數(shù)： 2/24頁(yè)
文件大?。?/td> 220K
代理商： A8259
58
Altera Corporation
a8259 Programmable Interrupt Controller Data Sheet
Table 1
describes the input and output ports of the
a8259
.
Note:
(1)
The interrupt request signals can be set as active high or positive-edge-triggered via bit 3 of Initialization Command
Word (ICW) 1 (see
“ICW 1” on page 62
for more information).
Table 1. a8259 Ports
Name
Type
Polarity
Description
nmrst
Input
Low
Master reset. When
default state. The
Clock. All registers are clocked on the positive edge of the clock.
Chip select. When low, this signal enables the
register access to and from the
a8259
Write control. When this signal is low (and
write transactions to the
a8259
.
Read control. When this signal is low (and
read transactions from the
a8259
Address. This signal serves as a register selector when writing to and
reading from internal
a8259
registers.
Interrupt acknowledge. This signal serves as the primary handshake
between the
a8259
and microprocessor during an interrupt service cycle.
Slave processor. This signal indicates that the
as a slave. However, this signal is ignored when the
as a single device. This signal should also be ignored in buffered mode.
Cascade data bus. These bus signals act as a cascade mode control to a
slave
a8259
. If the
a8259
is configured as a master, the bus should be
driven low.
Interrupt request. These are eight maskable, prioritized interrupt service
request signals.
Data bus. This bus inputs data when writing to internal
Interrupt. This signal indicates that the
service request.
Cascade data bus. These bus signals act as cascade mode control, and
should be connected to the
casin[2..0]
the
a8259
is configured as a master, the
Cascade directional bus enable. This signal is intended as a tri-state enable
signal to external bidirectional I/O buffers on the cascade control bus.
Data bus. The output data when reading from internal
Data enable. This signal indicates that a read cycle is being performed on
an internal
a8259
register, and it is intended as a tri-state enable to
external bidirectional I/O buffers.
nmrst
a8259
is asserted, all internal registers assume their
is idle, awaiting initialization.
clk
Input
Input
–
ncs
Low
nwr
and
nrd
signals and
.
nwr
Input
Low
ncs
signal is also low), it enables
nrd
Input
Low
ncs
signal is also low), it enables
.
a0
Input
High
ninta
Input
Low
nsp
Input
Low
a8259
should be configured
a8259
is configured
casin[2..0]
Input
High
ir[7..0]
Inputs
High
(1)
din[7..0]
Input
Output
–
a8259
registers.
int
High
a8259
has made an unmasked
casout[2..0]
Output
High
bus of a slave
casout[2..0]
a8259
bus is ignored.
. When
cas_en
Output
High
dout[7..0]
Output
Output
–
a8259
registers.
nen
Low
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