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參數(shù)資料
| 型號： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 17/24頁 |
| 文件大小： | 220K |
| 代理商： | A8259 |
Altera Corporation
73
a8259 Programmable Interrupt Controller Data Sheet
Note:
(1)
T7 through T3 derive from the contents of ICW 2 (bits 4 through 7).
6.
In AEOI mode, the ISR bit is reset on the rising edge of the last
ninta
pulse. When not in AEOI mode, an appropriate EOI
command is issued to end the interrupt sequence.
Figure 7
shows timing waveforms for the single-byte interrupt sequence
mode.
Figure 7. Single-Byte Interrupt Sequence Mode Timng Waveforms
X indicates “Dont Care.” VD indicates “Vector Data.”
Table 20. Contents of the Interrupt Vector Bytes
Note (1)
ir
dout7
dout6
dout5
dout4
dout3
dout2
dout1
dout0
7
6
5
4
3
2
1
0
T7
T7
T7
T7
T7
T7
T7
T7
T6
T6
T6
T6
T6
T6
T6
T6
T5
T5
T5
T5
T5
T5
T5
T5
T4
T4
T4
T4
T4
T4
T4
T4
T3
T3
T3
T3
T3
T3
T3
T3
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
X
X
VD
dout[7..0]
clk
Level-triggered
interrupt request
int
ninta
Edge-triggered
interrupt request
Level-triggered interrupt
request is clocked by the
falling edge of ninta.
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