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參數(shù)資料
| 型號(hào)： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 220K |
| 代理商： | A8259 |
64
Altera Corporation
a8259 Programmable Interrupt Controller Data Sheet
ICW 3
If SINGLE is low, ICW 3 must be initialized. Input data for ICW 3 is sent
via the
din[7..0]
bus, and data is clocked by the rising edge of
clk
.
ICW 3 is deselected with the next falling edge of the
nwr
signal.
The meaning of the ICW 3 contents depends on whether the
a8259
is
configured as a master or slave.
Table 5
describes the ICW 3 register
format for the
a8259
configured as a master.
Table 6
describes the ICW 3 register format when the
a8259
is configured
as a slave.
At this point in the initialization process, the next register selected
depends on whether bit 0 of ICW 1 is high. If bit 0 of ICW 1 is high, ICW 4
is selected (see
“ICW 4” on page 65
). If bit 0 is low, ICW 4 is skipped and
the
a8259
is ready to accept interrupts.
Table 5. ICW 3 Register Format (a8259 Master Configuration)
Bit
Mnemonic
Description
0
1
2
3
4
5
6
7
S0
S1
S2
S3
S4
S5
S6
S7
These bits are slave inputs. When high, each bit
indicates that the corresponding interrupt request line is
a cascaded slave input. For instance, if S2 is high, the
ir2
pin is treated as a slave input and receives data
from the
int
signal of another
a8259
.
Table 6. ICW 3 Register Format (a8259 Slave Configuration)
Bit
Mnemonic
Description
0
1
2
3
4
5
6
7
ID0
ID1
ID2
0
0
0
0
0
Slave identification. These bits set the slave ID for the
a8259
.
These bits are not used when the
a8259
is configured
as a slave, and they should be low.
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