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參數(shù)資料
| 型號： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 220K |
| 代理商： | A8259 |
78
Altera Corporation
a8259 Programmable Interrupt Controller Data Sheet
2.
The microprocessor responds to the vector opcode by sending two
more
ninta
pulses. The slave sets the appropriate ISR bit on the
falling edge of the second
ninta
pulse. Simultaneously, the slave’s
IRR bit is reset. The falling edge of the second
ninta
pulse also
causes the slave to place the lower eight interrupt vector address bits
on the slave’s
dout[7..0]
bus. The upper eight interrupt vector
address bits are released on the falling edge of the third
ninta
pulse.
3.
Two EOI commands must be issued to end the interrupt sequence:
one to the master and the other to the slave.
Single-Byte Interrupt Sequence in Cascade Mode
In a single-byte interrupt sequence in cascade mode, the handshaking
between the
int
and
ninta
signals is as follows:
1.
The master sets the ISR bit that corresponds to the slave input on the
falling edge of the first
ninta
pulse. The master also simultaneously
resets the IRR bit and no data is driven onto the
dout[7..0
] bus for
this cycle. The master enables the slave by placing the slave’s
address on the
casout[7..0]
bus at the rising edge of the first
ninta
pulse.
2.
The microprocessor issues a second
ninta
pulse. The slave sets the
corresponding ISR bit on the falling edge of the second
ninta
pulse.
Simultaneously, the slave’s IRR bit is reset. The slave drives the eight
interrupt vector address bits onto the
dout[7..0]
bus.
3.
Two EOI commands must be issued to end the interrupt sequence:
one to the master and one to the slave.
The slave’s address will remain on the
casout[2..0]
bus until the
rising edge of the last
ninta
pulse.
Special Fully Nested Mode
This mode is used in conjunction with the cascade mode to preserve the
priority structure within each slave. To operate in this mode, only bit 1 of
ICW 4 of the master should be high. The slaves are configured in normal
fully nested mode. When a slave is in service, it will not be locked out of
the master’s priority logic; the master can recognize interrupts from
higher priority sources within that slave.
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