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參數資料
| 型號： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數： | 14/24頁 |
| 文件大?。?/td> | 220K |
| 代理商： | A8259 |
70
Altera Corporation
a8259 Programmable Interrupt Controller Data Sheet
Interrupt
Sequencing
The
a8259
supports two interrupt sequencing modes:
I
I
3-byte interrupt sequence mode
Single-byte interrupt sequence mode
3-Byte Interrupt Sequence Mode
The 3-byte interrupt sequence mode provides a 24-bit interrupt vector.
The interrupt sequence for this mode is as follows:
1.
One or more of the interrupt request signals (
ir[7..0]
) are high,
which sets the corresponding bit in the IRR.
2.
The
a8259
checks the priority and masks for the interrupt, and if
appropriate, sets the
int
signal.
3.
The microprocessor responds by asserting
ninta
to the
a8259
.
4.
The
a8259
latches the interrupt request signals on the falling edge
of the
ninta
signal (when level-triggered). The
a8259
sets the
corresponding bit in the IRR on the following rising edge of
ninta
.
Simultaneously, the bit in the IRR is reset. The
a8259
places a fixed
vector opcode of binary
11001101
on the
dout[7..0]
bus while
the
ninta
signal is low. The vector opcode indicates that the
following two bytes will contain the interrupt vector.
5.
The microprocessor responds to the vector opcode by sending two
more
ninta
pulses. The falling edge of the first
ninta
pulse causes
the lower eight interrupt vector address bits to be placed on the
dout[7..0]
bus. The contents of the lower eight bits depend on the
value of the address interval bit (bit 2 of ICW 1). See
Tables 17
and
18
.
Table 16. ISR Format
Bit
Decode
0
1
2
3
4
5
6
7
ISR0
ISR1
ISR2
ISR3
ISR4
ISR5
ISR6
ISR7
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