參數(shù)資料
型號: ACE9050
廠商: Mitel Networks Corporation
英文描述: System Controller and Data Modem Advance Information
中文描述: 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器進展信息
文件頁數(shù): 11/52頁
文件大小: 390K
代理商: ACE9050
ACE9050
11
ACEBus Timing Cycle Conditions
Input clock frequency, XIN = 8·064MHz.
Worst case Timings:
T
AMB
=
2
40
°
C to
1
85
°
C, V
DD
=
1
3·6V to
1
5·5V
Typical timings:
T
AMB
=
1
25
°
C, V
DD
=
1
3·75V
SynthBus
(Note: The SynthBus is not required when the ACE9050 is used as part of the ACE Chipset)
t
D17
V
CL
H
SYNTHCLK
SYNTHDATA
DTFG
LATCH
D1-7
D1-6
D3-1
D3-0
t
CL
H
t
CL
L
t
CL
H
LA
H
t
LA
H
t
DA
V
CL
H
t
CL
H
DA
I
Fig.11 SynthBus timing diagram
SynthBus Timing Cycle Conditions
Input clock frequency, XIN = 8·064MHz.
Worst case Timings:
T
AMB
=
2
40
°
C to
1
85
°
C, V
DD
=
1
3·6V to
1
5·5V
Typical timings:
T
AMB
=
1
25
°
C, V
DD
=
1
3·75V
491
488
491
491
491
0·099
0
14
14
Characteristic
Value
Typ.
Max.
Min.
Programmable width
496
496
496
Conditions
Units
Symbol
TRANSMIT
Clock high to Data bus driven
Data set-up time
Data hold time
Clock high to Latch high
Latch width 0 and 1
Latch width 3
Clock low
Clock high
Clock high to data line tristate
RECEIVE
Data set-up time
Data hold time
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
12·59
5
t
CL
H
DA
t
DA
V
CL
H
t
CL
H
DA
I
t
CL
H
LA
H
t
PW
01
t
PW
3
t
CL
L
t
CL
H
t
CL
H
DA
Z
t
DA
V
CL
L
t
CL
L
DA
I
Table 6 ACEBus Read and Write timings
>0
Characteristic
Value
Typ.
Max.
Min.
3·9
4·0
4·97
952
3·99
3·93
Conditions
Units
Symbol
First data bit set-up time
Data bit set-up time (except first)
Data hold time
Clock high to latch high
Latch width
Clock low
Clock high
μ
s
μ
s
μ
s
μ
s
ns
μ
s
μ
s
7·84
t
D17
V
CL
H
t
DA
V
CL
H
t
CL
H
DA
I
t
CL
H
LA
H
t
LA
H
t
CL
L
t
CL
H
Table 7 SynthBus timing
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