參數(shù)資料
型號(hào)： ACE9050
廠(chǎng)商： Mitel Networks Corporation
英文描述： System Controller and Data Modem Advance Information
中文描述： 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器進(jìn)展信息
文件頁(yè)數(shù)： 45/52頁(yè)
文件大小： 390K
代理商： ACE9050
ACE9050
45
Block Descriptions
ATO Timer
The ATO timer is a 30 second resetable counter. If the ATO
counter reaches 30 seconds, an ATO Reset is generated. The
counter is reset by the following actions:
(a) External MRN Reset
(b) Accepted Processor Write to the RESATO register
The levels of the two external signals RXCD (pin 100) and
TXPOW (pin 61) are used to determine whether a processor
Write to RESATO is accepted or not, as shown in Table 106.
RXCD
0
0
1
1
Accepted
Denied
Accepted
Accepted
RESATO access
TXPOW
0
1
0
1
NOTE: The CPU cannot tell whether a hardware access has been
accepted or not.
Table 106
The RXCD input is filtered prior to use in the ATO Timer logic
by the RXCD Filter.
The ATO timer is NOT reset by Watchdog reset.
ATO Reset
When the AT0 Times Out the ATO reset circuit is trigered and
the following occurs:
(a) A Time Out Interrupt is generated.
(b) If the POFFN is high it will be driven low.
The Time Out interrupt is generated at least 1 second before
the POFFN is driven low. This is to give the processor time to
clean up before power is removed. The processor cannot
prevent the ATO reset at this stage.
The ACE9050 design assumes that the ATO Reset will
remove power from the phone system. If the system is designed
in such away that power is not removed from the ACE9050 the
POFFN pin is only guaranteed to stay low for approximately 1
second. The state of the internal circuitry is not guaranteed after
an ATO Reset.
RXCD Filter
The purpose of the filter is to smooth out short glitches in the
RXCD input. The filter waits for 1 second of RXCD becoming
high before the filter output is asserted. Once the output has been
asserted for more than 1 second, if the RXCD goes low for more
that 1 second the filter output will go low.
The filter hardware consists of a 10-bit up-down counter
clocked at 492Hz. If the RXCD nput s high the counter ncrements.
If it is low the counter decrements. Thus, assuming the counter
begins at zero, with a fixed high on the RXCD the counter’s MSB
will assert after 1 second and will overflow after approximately 2
seconds. When the counter overflows and RXCD is high it will
continue to hold the maximum count value and conversely, when
it reaches zero and RXCD is low, it will contain zero. The MSB
of the counter is the filter output which is fed to the ATO.
Programming Guide
Although the processor only needs to access the ATO
register once every 30 seconds to prevent the reset, the access
should occur more frequently. This would ensure a spurious
error condition unfortunately timed would not cause an ATO turn-
off. Servicing the ATO with the Watchdog would be the sensible
approach.
相關(guān)PDF資料
PDF描述
ACFA-450 AM CERAMIC FILTERS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ACE9050D/IG/GP2N 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk
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