參數(shù)資料
型號(hào)： ACE9050
廠商： Mitel Networks Corporation
英文描述： System Controller and Data Modem Advance Information
中文描述： 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器進(jìn)展信息
文件頁(yè)數(shù)： 28/52頁(yè)
文件大?。?/td> 390K
代理商： ACE9050
ACE9050
28
I2C_CCR Clock Control Register:
Write
This register is write only, the seven LSBs control the clock
frequency on the I
2
C bus when in master mode. The register is
cleared to 0 when the I
2
C is reset.
Table 43
Position
D7
D6
D5
D4
D3
D2
D1
D0
Bit
-
m3
m2
m1
m0
n2
n1
n0
The frequency of the SCL clock is given by:
f
SCL
=
10
3
(m
1
1)
3
2
n
f
CLK
Where:
f
SCL
is the I
2
C bus clock frequency,
f
CLK
is 8·064 MHz,
m is the value stored in CCR D[6: 3] and
n is the value stored in CCR D[2:0]
I2C_ADDR Slave Address:
Read/Write
This register sets the slave address of the ACE9050 I
2
C. This
is only valid when the I
2
C is in Slave mode, allowing the system
designer to select the required Slave address and prevent
contentions. The register is cleared to 0 when the ACE9050 I
2
C
is reset.
Position
D7
D6
D5
D4
D3
D2
D1
D0
Description
Table 44
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
GCE
Bit
Slave address 1st bit
Slave address 2nd bit
Slave address 3rd bit
Slave address 4th bit
Slave address 5th bit
Slave address 6th bit
Slave address 7th bit
General Call address enable
SLA6 - SLA0 sets the 7-bit address. SLA6 corresponds to the
first bit received from the I
2
C bus after a start condition. When the
ACE9050 I
2
C receives this address after a START condition it
will enter Slave mode. If GCE is set to one then the I
2
C will also
recogonise the General Call Address.(00
H
).
I2C_DATA Data Register:
Read/Write
This register contains the data byte to be transmitted or the
data byte which has just been received.
In transmit mode the byte is sent MSB first, in receive mode
the first bit received will be in the MSB of the register. After each
byte is transmitted this register will contain the byte that was
actually present on the bus. Therefore in the case of lost
arbitration this register will contain the received byte.
Clock Synchronisation
If another device on the I
2
C bus drives the clock line when the
ACE9050 I
2
C s n master mode the ACE9050 I
2
C will synchronise
its clock to the I
2
C bus clock. The high period of the clock will be
determined by the device that generates the shortest high clock
period. The low period of the clock will be determined by the
device that generates the longest low clock period.
A slave may stretch the low period of the clock to slow down
the bus Master. The low period may also be stretched for
handshaking purposes. This can be done after each bit transfer
or each byte transfer. The ACE9050 I
2
C will stretch the clock
after each byte transfer until the IFLG bit in the I2C_CNTR
register is cleared.
Bus Arbitration
In master mode the ACE9050 I
2
C will check that each
transmitted logic 1 appears on the I
2
C bus as a logic 1. If another
device on the bus overrules and pulls the SDA line low arbitration
is lost. If arbitration is lost during the transmission of a data byte
or a not acknowledged bit is received the ACE9050 I
2
C will return
to the idle state. If arbitration is lost during the transmission of an
address the ACE9050 I
2
C will switch to slave mode so that it can
recognise its own slave address or the general call address.
Bus and Internal Clock Speeds
The I
2
C bus is defined for bus clock speeds up to 100k bits/
s. The clock speed generated by the ACE9050 I
2
C in master
mode is determined by the I2C_CCR register.
All signals within the ACE9050 I
2
C are synchronised to an
internal main clock (MCLK).
The frequency of this clock is given by:
Bits
[7:0] Read
[7:0] Write
RXData
TXData
Data received
Data to transmit
Name
Description
Table 45
If the ACE9050 I
2
C is used in systems where there are
other masters on the I
2
C bus then the frequency of MCLK
should not be less than 500 kHz to prevent the ACE9050
I
2
C from missing a START condition sent by another
master.
Modes of Operation
The following section details the operation of the
ACE9050 I
2
C in the four possible modes of I
2
C transfer,
namely: Master Transmit, Master Receive, Slave Transmit
and Slave Receive.
Master Transmit
In the master transmit mode the ACE9050 I
2
C will
transmit a number of bytes to a slave receiver. Before the
master transmit mode can be entered the I2C_CNTR
register should be initialised as shown in Table 46, where
X is either 0 or 1.
Where:
f
MCLK
is the MCLK (main clock) clock frequency,
f
CLK
is 8·064 MHz and
m is the value stored in I2C_CCR D[6: 3]
f
MCLK
=
f
CLK
(m
1
1)
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