參數(shù)資料
型號(hào)： ACE9050
廠商： Mitel Networks Corporation
英文描述： System Controller and Data Modem Advance Information
中文描述： 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器進(jìn)展信息
文件頁(yè)數(shù)： 14/52頁(yè)
文件大?。?/td> 390K
代理商： ACE9050
ACE9050
14
The ROM code has a time out function so that if a valid start
code is not detected on the SCI normal code operation will
begin. The ROM code is fully described in the Internal ROM
Boot Block section.
4. TEST MODE
Test mode increases the efficiency of volume testing of the
part. Pin 1, TESTN, should be hardwired to V
DD
.
5. POWER DOWN MODES
To reduce overall power consumption, selective power down
of various blocks is available under software control. In the power
down state each block will go to a predetermined logic state. The
following power reduction features are included:
Bus Interface (CSEPN = 1 and Address = 3FFF)
8·064 MHz external Clock Off
1·008 MHz external Clock Off
AMPS/TACS Modem power down
ACE Serial Chip Interface Power down
CPU Sleep Mode
Crystal Oscillator Off
1MHz/2MHz Bus speed
FUNCTIONAL DESCRIPTIONS
1. ACE9050 6303R DESCRIPTION
General Description
The embedded processor in the ACE9050 is functionally
equivalent to a generic 6303R micro. This data sheet outlines the
functionality of the embedded processor, detailing its operation
with the internal peripheral circuitry. It is not intended as a
programmers guide for a 6303. If further information is required
the following publications are recommended:
HITACHI 8-bit single-Chip Microcomputer Data Book
Sept.1989
Motorola Microprocessors Data Manual
Macro Assemblers Reference Manual, Motorola
Semiconductors MC68MASR(D)
The 6303 is an 8-bit processing unit which has a completely
compatible instruction set with the 6301. It has object code
upwardly compatible with the HD6300, HD6801 and HD6802.
The ACE9050 has 6016 bytes of internal RAM (the 6303R
has 128 bytes). Other features are: a Serial communications
interface (SCI or UART), a 16-bit timer, 8-bit I/O port and a 5-bit
I/O port (only 2 are bonded out from the ACE9050). The bus
speed can be configured to 1·008 in Normal mode or 2·016MHz
in Turbo mode.
The ACE9050 has an Emulation mode whereby its internal
6303 is bypassed and the peripheral functions may be driven
externally by a standard 6303 ICE.
ACE9050 6303R Pin Description
The ACE9050 6303 is embedded in a kernel which interfaces
to the rest of the circuitry. Table 12 describes the internal
connections to the ACE9050 6303. In Emulation mode, none of
the output pins drive the internal buses.
Clock
The CPU Clock is provided from the Clock Generator Circuit
in the ACE9050. This clock is either 1·008MHz or 2·016MHz. It
is not further divided down in the 6303, so this clock frequency
is the same as the processor bus speed. Refer to the Clock
Generator section for details of how to configure the internal
Name
V
DD
V
SS
XTAL
External
E
NMI
IRQ
RES
Port2 [0]
Port2 [1]
Port2 [2]
Port2 [3]
Port2 [4]
Port1 [7:0]
Addr [15:8]
D/A [7:0]
R/W
AS
STBY
*
Port2 bits 0 and 1 must be configured as inputs in the 6303 to use the
IFC and Baud rate generator functions.
Table 12 Generic 6303 I/O mapping
clocks.
I/O
Description
I
I
-
-
I
-
I
I
I/O
*
-
I/O
*
I/O
I/O
I/O
O
I/O
O
O
-
Internal power supply
Internal Ground
Not connected
Not Used (System Clock Driven
into E directly)
System Clock IP
Not used: Tied to VDD
Connected to Interrupt Control block
and IRQN pin
Connected to Internal Reset MRI
Internally connected to IFC Counter
Not connected
Internally connect to Baud Clk
External Pin (SCI I/P or Port2)
External Pin (SCI O/P or Port2)
External Pin (Port1 I/0 Access)
Connected to internal address Bus
Internally connected to Buses
Connected to internal logic and R/W pin
Connected to internal logic
Standby mode disabled = V
DD
Port 1
This is an eight bit I/O port with the direction of each bit being
defined by the data direction register DDR1 as given in Table 13.
The Port can be accessed for read and write via the Port1
register. The output buffers have tristate capability, being high
impedance when used as inputs. When the processor is reset
these are high impedance. Two pins (Bits 3 and 4) associated
with this port are also used as I/0 from the I
2
C interface on the
ACE9050. This is configured by Port 5 bit 2. The 6303 is internally
configured to mimic Multiplexed mode of operation, so this port
cannot be configured to output the lower address bits. The
ACE9050 has dedicated pins for this purpose.
Associated Registers
Port 2
This is a five-bit I/O port with the direction of each bit being
defined by the data direction register DDR2. Only bit 3 and bit 4
are connected to external pins. This allows access to the I/O port
and Serial Interface functions. Bit 0 and bit 2 are internally
connected to the IFC and Baud clock. They must be configured
as inputs to use these functions. Bit 0 and bit 2 are not externally
accessible.
Name
DDR1
Bits [7: 0]
Port 1
Bits [7:0]
Description
1: Sets corresponding Port line to output
0: Sets corresponding Port line to input
Read and Write access to Port 1
Table 13 Port 1 associated registers
相關(guān)PDF資料
PDF描述
ACFA-450 AM CERAMIC FILTERS
ACFA-455 AM CERAMIC FILTERS
ACFA-459 AM CERAMIC FILTERS
ACFA-468 AM CERAMIC FILTERS
ACFJW-450A AM CERAMIC FILTERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ACE9050C/IW/FP1N 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk
ACE9050C/IW/FP1Q 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk
ace9050c/iw/fp8q 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
ace9050d/ig/gp1n 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
ACE9050D/IG/GP2N 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*