參數(shù)資料
型號(hào): ACE9050
廠商: Mitel Networks Corporation
英文描述: System Controller and Data Modem Advance Information
中文描述: 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器進(jìn)展信息
文件頁數(shù): 34/52頁
文件大?。?/td> 390K
代理商: ACE9050
ACE9050
34
MODPRT1 (continued)
Read
(Table 64)
Bit
Function
Not used
0 = Busy/idle bit = 0
1 = Busy/idle bit = 1
Bits [5:4]: SAT generator
00 = 5·97kHz
01 = 6·00kHz
10 = 6·03kHz
11 = No SAT received
Number of Data bits in a word that
have exceeded the pre-set Squelch
threshold
7
6
[5:4]
[3:0]
Name
-
B_I
SCCRX [1:0]
SQRX [3:0]
Table 64
Bit
Function
Data byte to transmit
[7:0]
Name
TXD [7:0]
Table 65
MODPRT2
This is a read/write port used for data transfer
Write
(Table 65)
Read
(Table 66)
Bit
Function
Received Data byte (note 1)
[7:0]
Name
RXD [7:0]
NOTE 1.When VC_CCN and ENWS = 0, busy/idle bits are extracted
from the data stream and are not present in RXD.
Table 66
Interrupts
The modem has 4 interrupt lines which feed into the Internal
Interrupt Control block. The interrupts can be read, reset and
individually masked in this block
IRQ-RX
Bit3
This interrupt is generated every time the data (RXD [7:0])
and squelch values (SQRX [3:0]) are updated. This will be
approximately every 800
μ
s for AMPS and 1ms for TACS. If busy/
idle bits are extracted, these times will vary by a maximum of one
bit period.
IRQ-BI-SAT
Bit5
This interrupt has a dual function, dependent on whether the
Modem is set up for a control channel or a voice channel.
On a control channel the interrupt occurs every time the busy/
idle bit B_I is updated in MODPORT1. This will occur nominally
every 1ms in an AMPS system and 1·25ms in TACS.
On a voice channel this interrupt indicates there is an updated
SAT value present in SCCRX. This will occur every 10 to 12ms.
IRQ-WS
Bit6
This interrupt occurs every time the 11-bit Barker code is
detected in the incoming data stream. Refer the Word Sync
Detector for more details.
IRQ-TX
Bit7
This interrupt occurs every time the first bit of a byte is
transmitted from the Modem Transmitter. The software must
ensure that the data in TXD is valid prior this interrupt. When
enabled it will generate an interrupt every 800
μ
s for AMPS and
1ms for TACS. The Data transmission sequence is discussed in
more detail in the Modem Transmitter section.
Fig. 21 Modem discriminator
Control Block
The Modem can be confiqured for either AMPS or TACS
systems. Various clocks and timing blocks are configured
depending on whether the data has a 10kHz or an 8kHz Bit rate
for AMPS/TACS respectively. The Modem can also be entirely
reset under software control.
If the Modem is not required the clock to the associated
circuitry can be stopped, thus reducing the current consumption
of the ACE9050.
Discriminator
(Fig. 21)
The Discriminator uses a digital delay technique. The ncominq
signal is first sampled at 504kHz. This means the input can either
be the 450kHz IF at CMOS levels or the 54kHz output from the
ACE9030; it makes no difference to the operation of the
discriminator.
MODEM BLOCK DESCRIPTIONS
In the ACE9030 the signal is initially sampled at 504kHz,
which is below the Nyquist frequency, so effectively a mixing
function occurs. 504kHz mixed with 450kHz gives a frequency
component at 54kHz. Further sampling of the signal at 504kHz
in the ACE9050 then has no effect.
The signal is then passed through a delay line of 12 D-type
flip-flops, clocked at 504 kHz, giving a delay of 23·8
μ
s, or
1·286 nominal 54kHz cycles. The non-delayed and delayed
signals are then EXORed together, which produces a digital
version of the analog equivalent FM demodulator: a 90
degree phase shifter and mixer. The ACE9030 contains a
similar discriminator, optimised for the speech content of the
signal. The ACE9030 data sheet contains a full description of
the operation of such a circuit.
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
AFC/RXDATA
504kHz
MODPRT1 [4]: LF1_2
MODPRT1 [5]: RXDINV
C1008
DISCRIMINATOR ENABLE/BYPASS
RXDATA INVERT/NOT INVERT
1
2
11
12
TO DATA
DECODER
4
2
RE-SYNC
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