- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8580 > AD5363BSTZ-REEL (Analog Devices Inc)IC DAC 14BIT 8CH SERIAL 52-LQFP PDF資料下載
參數(shù)資料
| 型號： | AD5363BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 8CH SERIAL 52-LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,500 |
| 設(shè)置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 209mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應商設(shè)備封裝： | 52-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | * |
| 配用： | EVAL-AD5363EBZ-ND - BOARD EVALUATION FOR AD5363 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
AD5362/AD5363
Rev. A | Page 18 of 28
OUTPUT AMPLIFIER
Because the output amplifiers can swing to 1.4 V below the
positive supply and 1.4 V above the negative supply, this limits
how much the output can be offset for a given reference voltage.
For example, it is not possible to have a unipolar output range
of 20 V, because the maximum supply voltage is ±16.5 V.
CLR
DAC
CHANNEL
OFFSET
DAC
OUTPUT
R6
10k
R2
20k
S3
S2
S1
R4
60k
R3
20k
SIGGNDx
R5
60k
R1
20k
05
76
2-
0
22
Figure 23. Output Amplifier and Offset DAC
Figure 23 shows details of a DAC output amplifier and its connec-
tions to the offset DAC. On power-up, S1 is open, disconnecting
the amplifier from the output. S3 is closed, so the output is pulled
to SIGGNDx (R1 and R2 are greater than R6). S2 is also closed to
prevent the output amplifier from being open-loop. If CLR is low at
power-up, the output remains in this condition until CLR is taken
high. The DAC registers can be programmed, and the outputs
assume the programmed values when CLR is taken high. Even if
CLR is high at power-up, the output remains in this condition
until VDD > 6 V and VSS < 4 V and the initialization sequence has
finished. The outputs then go to their power-on default value.
TRANSFER FUNCTION
The output voltage of a DAC in the AD5362/AD5363 is depen-
dent on the value in the input register, the value of the M and C
registers, and the value in the offset DAC.
AD5362 Transfer Function
The input code is the value in the X1A or X1B register that is
applied to the DAC (X1A, X1B default code = 32,768).
DAC_CODE = INPUT_CODE × (M + 1)/216 + C 215
where:
M = code in gain register default code = 216 – 1.
C = code in offset register default code = 215.
The DAC output voltage is calculated as follows:
VOUT = 4 × VREF × (DAC_CODE (OFFSET_CODE ×
4))/216 + VSIGGND
where:
DAC_CODE should be within the range of 0 to 65,535.
For 12 V span, VREF = 3.0 V.
For 20 V span, VREF = 5.0 V.
OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function because this DAC is a
14-bit device. On power-up, the default code loaded to the
offset DAC is 8192 (0x2000). With a 5 V reference, this gives
a span of 10 V to +10 V.
AD5363 Transfer Function
The input code is the value in the X1A or X1B register that is
applied to the DAC (X1A, X1B default code = 8192).
DAC_CODE = INPUT_CODE × (M + 1)/214 + C 213
where:
M = code in gain register default code = 214 – 1.
C = code in offset register default code = 213.
The DAC output voltage is calculated as follows:
VOUT = 4 × VREF × (DAC_CODE OFFSET_CODE)/
214 + VSIGGND
where:
DAC_CODE should be within the range of 0 to 16,383.
For 12 V span, VREF = 3.0 V.
For 20 V span, VREF = 5.0 V.
OFFSET_CODE is the code loaded to the offset DAC. On power-
up, the default code loaded to the offset DAC is 8192 (0x2000).
With a 5 V reference, this gives a span of 10 V to +10 V.
REFERENCE SELECTION
The AD5362/AD5363 have two reference input pins. The
voltage applied to the reference pins determines the output
voltage span on VOUT0 to VOUT7. VREF0 determines the
voltage span for VOUT0 to VOUT3 (Group 0), and VREF1
determines the voltage span for VOUT4 to VOUT7 (Group 1).
The reference voltage applied to each VREF pin can be differ-
ent, if required, allowing each group of four channels to have a
different voltage span. The output voltage range and span can
be adjusted further by programming the offset and gain
registers for each channel as well as programming the offset
DAC. If the offset and gain features are not used (that is, the M
and C registers are left at their default values), the required
reference levels can be calculated as follows:
VREF = (VOUTMAX VOUTMIN)/4
If the offset and gain features of the AD5362/AD5363 are used,
the required output range is slightly different. The selected
output range should take into account the system offset and
gain errors that need to be trimmed out. Therefore, the selected
output range should be larger than the actual, required range.
The required reference levels can be calculated as follows:
1.
Identify the nominal output range on VOUT.
2.
Identify the maximum offset span and the maximum gain
required on the full output signal range.
3.
Calculate the new maximum output range on VOUT,
including the expected maximum offset and gain errors.
4.
Choose the new required VOUTMAX and VOUTMIN, keep-
ing the VOUT limits centered on the nominal values. Note
that VDD and VSS must provide sufficient headroom.
5.
Calculate the value of VREF as follows:
VREF = (VOUTMAX VOUTMIN)/4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B4Z-MX-B1 | CONVERTER MOD DC/DC 2V 30W |
| AD5363BCPZ-REEL7 | IC DAC 14BIT 8CH SERIAL 56-LFCSP |
| VI-B4Z-MW-B1 | CONVERTER MOD DC/DC 2V 40W |
| VI-B4Y-MY-B1 | CONVERTER MOD DC/DC 3.3V 33W |
| AD5765CSUZ-REEL7 | IC DAC 16BIT 5V QUAD 32-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5365D/BIN/883B | 制造商:Analog Devices 功能描述:- Rail/Tube |
| AD536A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Circuit True RMS-to-DC Converter |
| AD536AJC/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RMS-to-DC Converter |
| AD536AJCHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Circuit True RMS-to-DC Converter |
| AD536AJCWE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RMS-to-DC Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復。