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參數(shù)資料
| 型號： | AD5363BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/29頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 8CH SERIAL 52-LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,500 |
| 設置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 8 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 209mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應商設備封裝： | 52-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | * |
| 配用： | EVAL-AD5363EBZ-ND - BOARD EVALUATION FOR AD5363 |
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AD5362/AD5363
Rev. A | Page 21 of
28
MONITOR FUNCTION
The AD5362/AD5363 contain a channel monitor function
that consists of an analog multiplexer addressed via the serial
interface, allowing any channel output to be routed to the
MON_OUT pin for monitoring using an external ADC. In
addition, two monitor inputs, MON_IN0 and MON_IN1,
are provided, which can also be routed to MON_OUT. The
monitor function is controlled by the monitor register, which
allows the monitor output to be enabled or disabled, and selects
a DAC channel or one of the monitor pins. When disabled, the
monitor output is high impedance so that several monitor
outputs can be connected in parallel with only one enabled at
a time. Table 10 shows the monitor register settings.
Table 10. Monitor Register Functions
F5
F4
F3
F2
F1
F0
Function
0
X
MON_OUT disabled
1
X
MON_OUT enabled
1
0
MON_OUT = VOUT0
1
0
1
MON_OUT = VOUT1
1
0
1
0
MON_OUT = VOUT2
1
0
1
MON_OUT = VOUT3
1
0
1
0
MON_OUT = VOUT4
1
0
1
0
1
MON_OUT = VOUT5
1
0
1
0
1
0
MON_OUT = VOUT6
1
0
1
0
1
MON_OUT = VOUT7
1
0
MON_OUT = MON_IN0
1
0
1
MON_OUT = MON_IN1
The multiplexer is implemented as a series of analog switches.
Because this could conceivably cause a large amount of current
to flow from the input of the multiplexer (VOUTx or MON_INx)
to the output of the multiplexer (MON_OUT), care should be
taken to ensure that whatever is connected to the MON_OUT
pin is of high enough impedance to prevent the continuous
current limit specification from being exceeded. Because the
MON_OUT pin is not buffered, the amount of current drawn
from this pin creates a voltage drop across the switches, which
in turn leads to an error in the voltage being monitored. Where
accuracy is important, it is recommended that the MON_OUT
pin be buffered. Figure 20 shows the typical error due to
MON_OUT current.
GPIO PIN
The AD5362/AD5363 have a general-purpose I/O pin, GPIO.
This pin can be configured as an input or an output and read
back or programmed (when configured as an output) via the
serial interface. Typical applications for this pin include moni-
toring the status of a logic signal, a limit switch, or controlling
an external multiplexer. The GPIO pin is configured by writing
to the GPIO register, which has the special function code of
When Bit F1 is set, the GPIO pin becomes an output and Bit F0
determines whether the pin is high or low. The GPIO pin can be
set as an input by writing 0 to both Bit F1 and Bit F0. The status
of the GPIO pin can be determined by initiating a read operation
using the appropriate bits in Table 17. The status of the pin is
indicated by the LSB of the register read.
POWER-DOWN MODE
The AD5362/AD5363 can be powered down by setting Bit 0 in
the control register to 1. This turns off the DACs, thus reducing
the current consumption. The DAC outputs are connected to
their respective SIGGNDx potentials. The power-down mode
does not change the contents of the registers, and the DACs
return to their previous voltage when the power-down bit is
cleared to 0.
THERMAL SHUTDOWN FUNCTION
The AD5362/AD5363 can be programmed to shut down the
DACs if the temperature on the die exceeds 130°C. Setting Bit 1
in the control register to 1 enables this function (see Table 16).
If the die temperature exceeds 130°C, the AD5362/AD5363
enter a thermal shutdown mode, which is equivalent to setting
the power-down bit in the control register. To indicate that the
AD5362/AD5363 have entered thermal shutdown mode, Bit 4
of the control register is set to 1. The AD5362/AD5363 remain
in thermal shutdown mode, even if the die temperature falls,
until Bit 1 in the control register is cleared to 0.
TOGGLE MODE
The AD5362/AD5363 have two X2 registers per channel, X2A
and X2B, which can be used to switch the DAC output between
two levels with ease. This approach greatly reduces the overhead
required by a microprocessor, which would otherwise need to
write to each channel individually. When the user writes to the
X1A, X1B, M, or C register, the calculation engine takes a certain
amount of time to calculate the appropriate X2A or X2B value.
If an application, such as a data generator, requires that the DAC
output switch between two levels only, any method that reduces
the amount of calculation time necessary is advantageous. For
the data generator example, the user needs only to set the high
and low levels for each channel once by writing to the X1A and
X1B registers. The values of X2A and X2B are calculated and
stored in their respective registers. The calculation delay,
therefore, happens only during the setup phase, that is, when
programming the initial values. To toggle a DAC output between
the two levels, it is only required to write to the relevant A/B
select register to set the MUX2 register bit. Furthermore,
because there are four MUX2 control bits per register, it is
possible to update eight channels with just two writes. Table 18
shows the bits that correspond to each DAC output.
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