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| 型號(hào)： | AD5363BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 8CH SERIAL 52-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 設(shè)置時(shí)間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 209mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應(yīng)商設(shè)備封裝： | 52-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | * |
| 配用： | EVAL-AD5363EBZ-ND - BOARD EVALUATION FOR AD5363 |
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AD5362/AD5363
Rev. A | Page 11 of
28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
52 51 50 49 48
43 42 41 40
47 46 45 44
14 15 16 17 18 19 20 21 22 23 24 25 26
1
2
3
4
5
6
7
8
9
10
11
13
12
39
38
37
36
35
34
33
32
31
30
29
28
27
NC
VO
U
T
4
VO
U
T
5
VO
U
T
6
VO
U
T
7
S
IGG
N
D
1
NC
LDAC
CLR
RESET
BIN/2SCOMP
BUSY
GPIO
MON_OUT
MON_IN0
NC
VDD
VSS
VREF1
NC
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
TEMP_OUT
MON_IN1
VREF0
NC
VSS
VDD
NC
NC = NO CONNECT
AG
N
D
DV
CC
SD
O
PE
C
SD
I
SC
L
K
SY
N
C
DV
CC
DG
N
D
NC
DG
N
D
PIN 1
INDICATOR
AD5362/
AD5363
TOP VIEW
(Not to Scale)
0
5
762
-00
7
PIN 1
INDICATOR
AD5362/
AD5363
TOP VIEW
(Not to Scale)
05
76
2-
0
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
5 16 17 18 19 20 21 22 23 24 25 26 27 28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
5
6 55 54 53 52 51 50 49 48 47 46 45 44 43
RESET
BIN/2SCOMP
BUSY
GPIO
MON_OUT
MON_IN0
NC
VDD
VSS
VREF1
NC = NO CONNECT
V
O
U
T
4
V
O
U
T
5
V
O
U
T
6
V
O
U
T
7
S
IG
G
N
D
1
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
NC
NC NC
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
TEMP_OUT
MON_IN1
VREF0
NC
VSS
VDD
C
L
R
L
D
A
C
A
G
N
D
G
N
D
V
C
S
D
O
P
E
C
S
D
I
S
C
L
K
S
Y
N
C
D
V
C
D
G
N
D
Figure 7. 52-Lead LQFP Pin Configuration
Figure 8. 56-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
LQFP
LFCSP
1
55
LDAC
Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section
for more information.
2
56
CLR
Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function
section for more information.
3
1
RESET
Digital Reset Input.
4
2
BIN/2SCOMP
Data Format Digital Input. Connecting this pin to DGND selects offset binary.
Setting this pin to 1 selects twos complement. This input has a weak pull-down.
5
3
BUSY
Digital Input/Open-Drain Output. BUSY is open drain when it is an output. See
the BUSY and LDAC Functions section for more information.
6
4
GPIO
Digital I/O Pin. This pin can be configured as an input or output that can be
read back or programmed high or low via the serial interface. When configured
as an input, this pin has a weak pull-down.
7
5
MON_OUT
Analog Multiplexer Output. Any DAC output, the MON_IN0 input, or the
MON_IN1 input can be routed to this output for monitoring.
8, 32
6, 34
MON_IN0,
MON_IN1
Analog Multiplexer Inputs. Can be routed to MON_OUT.
9, 10, 14, 20 to
27, 30, 39 to 42
7 to 11, 15, 16,
22 to 28, 31, 32,
41 to 44
NC
No Connect.
11, 28
12, 29
VDD
Positive Analog Power Supply; 9 V to 16.5 V for specified performance. These
pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
12, 29
13, 30
VSS
Negative Analog Power Supply; 16.5 V to 8 V for specified performance.
These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF
capacitors.
13
14
VREF1
Reference Input for DAC 4 to DAC 7. This reference voltage is referred to AGND.
34 to 37, 15 to 18
36 to 39, 17 to 20
VOUT0 to VOUT7
DAC Outputs. Buffered analog outputs for each of the eight DAC channels.
Each analog output is capable of driving an output load of 10 kΩ to ground.
Typical output impedance of these amplifiers is 0.5 Ω.
19
21
SIGGND1
Reference Ground for DAC 4 to DAC 7. VOUT4 to VOUT7 are referenced to this
voltage.
31
33
VREF0
Reference Input for DAC 0 to DAC 3. This reference voltage is referred to AGND.
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