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參數(shù)資料
| 型號： | AD5363BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 8CH SERIAL 52-LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,500 |
| 設(shè)置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 209mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應(yīng)商設(shè)備封裝： | 52-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | * |
| 配用： | EVAL-AD5363EBZ-ND - BOARD EVALUATION FOR AD5363 |
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AD5362/AD5363
Rev. A | Page 16 of
28
THEORY OF OPERATION
DAC ARCHITECTURE
The AD5362/AD5363 contain eight DAC channels and eight
output amplifiers in a single package. The architecture of a
single DAC channel consists of a 16-bit (AD5362) or 14-bit
(AD5363) resistor-string DAC followed by an output buffer
amplifier. The resistor-string section is simply a string of resistors,
of equal value, from VREF0 or VREF1 to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit (AD5362)
or 14-bit (AD5363) binary digital code loaded to the DAC
register determines at which node on the string the voltage is
tapped off before being fed into the output amplifier. The output
amplifier multiplies the DAC output voltage by 4. The nominal
output span is 12 V with a 3 V reference and 20 V with a 5 V
reference.
CHANNEL GROUPS
The eight DAC channels of the AD5362/AD5363 are arranged
into two groups of four channels. The four DACs of Group 0
derive their reference voltage from VREF0. The four DACs of
Group 1 derive their reference voltage from VREF1. Each group
has its own signal ground pin.
Table 7. AD5362/AD5363 Registers
Register Name
Word Length in Bits
Description
X1A (Group) (Channel)
16 (14)
Input Data Register A, one for each DAC channel.
X1B (Group) (Channel)
16 (14)
Input Data Register B, one for each DAC channel.
M (Group) (Channel)
16 (14)
Gain trim registers, one for each DAC channel.
C (Group) (Channel)
16 (14)
Offset trim registers, one for each DAC channel.
X2A (Group) (Channel)
16 (14)
Output Data Register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
X2B (Group) (Channel)
16 (14)
Output Data Register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
DAC (Group) (Channel)
Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable or directly writable.
OFS0
14
Offset DAC 0 data register: sets offset for Group 0.
OFS1
14
Offset DAC 1 data register: sets offset for Group 1.
Control
5
Bit 4 = overtemperature indicator.
Bit 3 = PEC error flag.
Bit 2 = A/B select.
Bit 1 = thermal shutdown.
Bit 0 = software power-down.
Monitor
6
Bit 5 = monitor enable.
Bit 4 = monitor DACs or monitor MON_INx pin.
Bit 3 to Bit 0 = monitor selection control.
GPIO
2
Bit 1 = GPIO configuration.
Bit 0 = GPIO data.
A/B Select 0
8
Bits [3:0] in this register determine whether a DAC in Group 0 takes its data from
Register X2A or Register X2B (0 = X2A, 1 = X2B).
A/B Select 1
8
Bits [3:0] in this register determine whether a DAC in Group 1 takes its data from
Register X2A or Register X2B (0 = X2A, 1 = X2B).
Table 8. AD5362/AD5363 Input Register Default Values
Register Name
AD5362 Default Value
AD5363 Default Value
X1A, X1B
0x8000
0x2000
M
0xFFFF
0x3FFF
C
0x8000
0x2000
OFS0, OFS1
0x2000
Control
0x00
A/B Select 0 and A/B Select 1
0x00
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