參數(shù)資料
型號: AD5363BSTZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 19/29頁
文件大小: 0K
描述: IC DAC 14BIT 8CH SERIAL 52-LQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1,500
設(shè)置時間: 20µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 雙 ±
功率耗散(最大): 209mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應(yīng)商設(shè)備封裝: 52-LQFP(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 8 電壓,單極;8 電壓,雙極
采樣率(每秒): *
配用: EVAL-AD5363EBZ-ND - BOARD EVALUATION FOR AD5363
AD5362/AD5363
Rev. A | Page 25 of 28
Table 17. Address Codes for Data Readback1
F15
F14
F13
F12
F11
F10
F9
F8
F7
Register Read
0
X1A register
0
1
X1B register
0
1
0
C register
0
1
Bit F12 to Bit F7 select the channel to be read back;
Channel 0 = 001000 to Channel 3 = 001011
Channel 4 = 010000 to Channel 7 = 010011
M register
1
0
1
Control register
1
0
1
0
OFS0 data register
1
0
1
OFS1 data register
1
0
1
0
Reserved
1
0
1
0
A/B Select Register 0
1
0
1
A/B Select Register 1
1
0
1
0
Reserved
1
0
1
0
1
Reserved
1
0
1
0
1
0
Reserved
1
0
1
0
1
GPIO read (data in F0)2
1 Bit F6 to Bit F0 are don’t cares for the data readback function.
2 Bit F6 to Bit F0 should be 0 for GPIO read.
Table 18. DACs Selected by A/B Select Registers
A/B Select
Register
F7
F6
F5
F4
F3
F2
F1
F0
0
Reserved
DAC 3
DAC 2
DAC 1
DAC 0
1
Reserved
DAC 7
DAC 6
DAC 5
DAC 4
1 If the bit is set to 0, Register X2A is selected. If the bit is set to 1, Register X2B is selected.
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