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參數(shù)資料
| 型號： | AD6636BBCZ1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁數(shù)： | 28/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636BBCZ1 |
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AD6636
Amplitude Dither
Amplitude dither can be used to improve spurious performance
of the NCO. Amplitude dither is enabled by writing Logic 1 in
the amplitude dither enable bit of the NCO control register of
the channel under consideration. Random amplitude is added
to the LSBs of the sine and cosine amplitudes, when this feature
is enabled. Amplitude dither improves performance by
randomizing the amplitude quantization errors within the
angular-to-Cartesian conversion of the NCO. This option
might reduce spurs at the expense of a slightly raised noise
floor. Amplitude dither and phase dither can be used together,
separately, or not at all.
NCO Frequency Hold-Off Register
When the NCO frequency registers are written by the
microport or serial port, data is passed to a shadow register.
Data can be moved to the main registers when the channel
comes out of sleep mode, or when a sync hop occurs. In either
event, a counter can be loaded with the NCO frequency hold-
off register value. The 16-bit unsigned integer counter starts
counting down, clocked by the input port clock selected at the
crossbar mux. When the counter reaches 0, the new frequency
value in the shadow register is written to the NCO frequency
register. Writing 1 in this hold-off register updates the NCO
frequency register as soon as the start sync or hop sync occurs.
See the Chip Synchronization section for details.
Phase Offset
The phase offset register can be written with a value that is
added as an offset to the phase accumulator of the NCO. This
16-bit register is interpreted as a 16-bit unsigned integer. A
0x0000 in this register corresponds to a 0 radian offset and a
0xFFFF corresponds to an offset of 2π × (1 1/2
16
) radians.
This register allows multiple NCOs (multiple channels) to be
synchronized to produce complex sinusoids with a known and
steady phase difference.
Hop Sync
A hop sync should be issued to the channel, when the channel’s
NCO frequency needs to be changed from one frequency to a
different frequency. This feature is discussed in detail in the
Chip Synchronization section.
Rev. 0 | Page 28 of 72
FIFTH-ORDER CIC FILTER
The signal processing stage immediately after the NCO is a CIC
filter stage. This stage implements a fixed-coefficient,
decimating, cascade integrated comb filter. The input rate to this
filter is the same as the data rate at the input port; the output
rate from this stage is dependent on the decimation factor.
cic
in
CIC
M
f
f
=
The decimation ratio, M
CIC
, can be programmed from 2 to 32
(only integer values). The 5-bit word in the CIC decimation
register is used to set the CIC decimation factor. A binary value
of one less than the decimation factor is written into this
register. The decimation ratio of 1 can be achieved by bypassing
the CIC filter stage. The frequency response of the filter is given
by the following equations. The gain and pass-band droop of
the CIC should be calculated by these equations. Both parame-
ters can be offset in the RCF stage.
5
1
)
+
(
1
1
2
1
)
(
×
=
Z
Z
z
H
CIC
CIC
S
M
5
)
+
(
SIN
SIN
2
1
)
(
π
×
=
×
in
in
f
CIC
f
S
f
f
M
f
H
CIC
where:
f
in
is the data input rate to the channel under consideration.
S
CIC
, the scale factor, is a programmable unsigned integer
between 0 and 20.
The attenuation of the data into the CIC stage should be
controlled in 6 dB increments. For the best dynamic range,
S
CIC
should be set to the smallest value possible (lowest attenuation
possible) without creating an overflow condition. This can be
accomplished safely using the following equation, where
input_level
is the largest possible fraction of the full-scale value
at the input port. This value is output from the NCO stage and
pipelined into the CIC filter.
(
2
CIC
CIC
(
input
OL
CIC
S
2
Bypass
The fifth-order CIC filter can be bypassed when no decimation
is required of it. When it is bypassed, the scaling operation is
not performed. In bypass mode, the output of the CIC filter is
the same as the input of the CIC filter.
CIC Rejection
Table 13 illustrates the amount of bandwidth as a percentage of
the data rate into the CIC stage, which can be protected with
various decimation rates and alias rejection specifications. The
maximum input rate into the CIC is 150 MHz (the same as the
maximum input port data rate). The data may be scaled to any
other allowable sample rate.
)
(
)
5
-
_
5
log
level
input
M
ceil
S
×
=
)
level
M
CIC
CIC
_
5
5
×
=
+
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD6636BC | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636BC/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 150 MSPS, Wide Band, Digital Down Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
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| AD6636CBCZ | 功能描述:IC DIGITAL DWNCONV 4CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
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