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參數資料
| 型號： | AD6636BBCZ1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數字下變頻器（DDC） |
| 文件頁數： | 41/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636BBCZ1 |
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AD6636
operation in the logarithmic domain. The rms samples obtained
are subtracted from the request signal level R specified in the
AGC desired level register, leaving an error term to be processed
by the loop filter, G(z).
Rev. 0 | Page 41 of 72
The user sets this programmable request signal level R accord-
ing to the output signal level that is desired. The request signal
level R is programmable from 0 dB to 23.99 dB in steps of
0.094 dB.
The request signal level should also compensate for errors, if
any, due to the CIC scaling, as explained previously in this
section. Therefore, the request signal level is offset by the
amount of error induced in CIC, given by
Offset
= 10 × log(
M
CIC
×
N
avg
)
S
CIC
× 3.01 dB
where
Offset
is in dB.
Continuing the previous example, this offset is given by
Offset
= 72.24 69.54 = 2.7 dB
So the request signal level is given by
dBFS
094
.
×
094
.
)
(
=
Offset
DSL
ceil
R
where:
R
is the request signal level.
DSL
(desired signal level) is the output signal level that the user
desires.
Therefore, in the previous example, if the desired signal level is
13.8 dB, the request level
R
is programmed to be 16.54 dB,
compensating for the offset.
This request signal level is programmed in the 8-bit AGC
desired level register. This register has a floating-point represen-
tation, where the 2 MSBs are exponent bits and the 6 LSBs are
mantissa bits. The exponent is in steps of 6.02 dB, and the
mantissa is in steps of 0.094 dB. For example, a value 10’100101
represents 2 × 6.02 + 37 × 0.094 = 15.518 dB.
The AGC provides a programmable second-order loop filter.
The programmable parameters gain 1 (K
1
), gain 2 (K
2
), error
threshold E, and pole P completely define the loop filter
characteristics. The error term after subtracting the request
signal level is processed by the loop filter, G(z). The open loop
poles of the second-order loop filter are 1 and P, respectively.
The loop filter parameters, pole P and gain K, allow the
adjustment of the filter time constant that determines the
window for calculating the peak-to-average ratio.
Depending on the value of the error term that is obtained after
subtracting the request signal level from the actual signal level,
either gain value, K
1
or K
2
, is used. If the error is less than the
programmable threshold E, K
1
or K
2
is used. This allows a fast
loop when the error term is high (large convergence steps
required) and a slower loop function when error term is smaller
(almost converged).
The open-loop gain used in the second-order loop G(z) is given
by one of the following equations:
K
=
K
1
,
if Error
<
Error Threshold
K
=
K
2
,
if Error
>
Error Threshold
The open-loop transfer function for the filter, including the gain
parameter, is
( )
(
)
2
1
1
1
1
+
+
=
Pz
z
P
Kz
G
If the AGC is properly configured in terms of offset in request
level, then there are no gains in the AGC loop except for the
filter gain
K
. Under these circumstances, a closed-loop
expression for the AGC loop is given by
( )
( )
G
( )
(
)
2
1
1
1
1
1
+
+
=
+
=
Pz
z
P
K
Kz
G
G
closed
The gain parameters K
1
, K
2
, and pole P are programmable
through AGC loop gain 1, 2, and AGC pole location registers
from 0 to 0.996 in steps of 0.0039 using 8-bit representation. For
example, 1000 1001 represent (137/256 = 0.535156). The error
threshold value is programmable between 0 dB and 96.3 dB in
steps of 0.024 dB. This value is programmed in the 12-bit AGC
error threshold register, using floating-point representation. It
consists of four exponent bits and eight mantissa bits. Exponent
bits are in steps of 6.02 dB and mantissa bits are in steps of
0.024 dB. For example, 0111’10001001 represents 7 × 6.02 + 137
× 0.024 = 45.428 dB.
The user defines the open-loop pole P and gain K, which also
directly impact the placement of the closed-loop poles and filter
characteristics. These closed-loop poles, P
1
, P
2
, are the roots of
the denominator of the previous closed-loop transfer function
and are given by
2
4
)
1
)
1
,
2
P
K
P
K
P
P
P
2
1
+
+
+
=
Typically, the AGC loop performance is defined in terms of its
time constant or settling time. In this case, the closed-loop poles
should be set to meet the time constants required by the AGC
loop.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD6636BC | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636BC/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 150 MSPS, Wide Band, Digital Down Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636CBC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD6636CBCZ | 功能描述:IC DIGITAL DWNCONV 4CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數目:1 增益:17dB 噪音數據:2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應商設備封裝:12-QFN-EP（3x3） |
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