參數(shù)資料
型號(hào)： AD6636BBCZ1
廠商： Analog Devices, Inc.
元件分類： 數(shù)字上／下變頻
英文描述： 150 MSPS Wideband Digital Down-Converter (DDC)
中文描述： 150MSPS的寬帶數(shù)字下變頻器（DDC）
文件頁(yè)數(shù)： 59/72頁(yè)
文件大?。?/td> 1629K
代理商： AD6636BBCZ1
AD6636
<9>: Channel 5 Data Ready Enable Bit. When this bit is set, the
Channel 5 data ready interrupt is enabled, allowing an interrupt
to be generated when Channel 5 BIST signature registers are
updated. When this bit is cleared, an interrupt cannot be
generated for this event.
Rev. 0 | Page 59 of 72
<8>: Channel 4 Data Ready Enable Bit. Similar to Bit <9> for
Channel 4.
<7>: Channel 3 Data Ready Enable Bit. Similar to Bit <9> for
Channel 3.
<6>: Channel 2 Data Ready Enable Bit. Similar to Bit <9> for
Channel 2.
<5>: Channel 1 Data Ready Enable Bit. Similar to Bit <9> for
Channel 1.
<4>: Channel 0 Data Ready Enable Bit. Similar to Bit <9> for
Channel 0.
<3>: ADC Port D Power Monitoring Enable Bit. When this bit is
set to Logic 1, the ADC Port D power monitoring interrupt is
enabled allowing an interrupt to be generated when ADC Port
D power monitoring registers are updated. When set to Logic 1,
the ADC Port D power monitoring interrupt is disabled.
<2>: ADC Port C Power Monitoring Enable Bit. Similar to
Bit <3> for ADC Port C.
<1>: ADC Port B Power Monitoring Enable Bit. Similar to
Bit <3> for ADC Port B.
<0>: ADC Port A Power Monitoring Enable Bit. Similar to
Bit <3> for ADC Port A.
INPUT PORT REGISTER MAP
ADC Input Control Register <27:0>
These bits are general control bits for the ADC input logic.
<27>: PN Active Bit. When this bit is set, the pseudorandom
number generator is active. When this bit is cleared, the PN
generator is disabled and the seed is set to its default value.
<26>: EXP Lock Bit. When this bit is set along with the PN
active bit, then the EXP signal for pseudorandom input is
locked to 000 (giving full-scale input). When this bit is cleared,
EXP bits for pseudorandom input are randomly generated input
data bits.
<25>: Port C Complex Data Active Bit. When this bit is set, the
data inputs on Ports C and D are interpreted as complex inputs
(Port C for the in-phase signal and Port D for the quadrature
phase signal). This complex input is passed on as the input from
ADC Port C. When this bit is cleared, the data on ADC Port C
and ADC Port D interpreted as real and independent input.
Note that complex input mode is available only in CMOS input
mode.
<24>: Port A Complex Data Active Bit. When this bit is set, the
data input on Ports A and B is interpreted as complex input
(Port A for the in-phase signal and Port B for the quadrature
phase signal). This complex input is passed on as input from
ADC Port A. When this bit is cleared, the data on ADC Port A
and ADC Port B is interpreted as real and independent input.
Note that complex input mode is available only in CMOS input
mode.
<23>: Channel 5 Complex Data Input Bit. When this bit is set,
Channel 5 gets complex input data from the source that is
selected by the crossbar mux select bits. When this bit is cleared,
Channel 5 receives real input data. (See Table 31.)
<22:20>: Channel 5 Crossbar Mux Select Bits. These bits select
the source of input data for Channel 5. (See Table 31.)
Table 31. Channel 5 Input Configuration
Complex Data
Input Bit
Select Bits
0
000
Crossbar Mux
Configuration
ADC Port A drives input
(real).
ADC Port B drives input
(real).
ADC Port C drives input
(real).
ADC Port D drives input
(real).
PN sequence drives input
(real).
Ports A and B drive
complex input.
Ports C and D drive
complex input.
PN sequence drives
complex input.
0
001
0
010
0
011
0
100
1
000
1
001
1
010
<19>: Channel 4 Complex Data Input Bit. Similar to Bit <23>
for Channel 4.
<18:16>: Channel 4 Crossbar Mux Select Bits. Similar to Bits
<22:20> for Channel 4.
<15>: Channel 3 Complex Data Input Bit. Similar to Bit <23>
for Channel 3.
<14:12>: Channel 3 Crossbar Mux Select Bits. Similar to Bits
<22:20> for Channel 3.
<11>: Channel 2 Complex Data Input Bit. Similar to Bit <23>
for Channel 2.
<10:8>: Channel 2 Crossbar Mux Select Bits. Similar to Bits
<22:20> for Channel 2.
相關(guān)PDF資料
PDF描述
AD6636BC 150 MSPS Wideband Digital Down-Converter (DDC)
AD6636CBCZ1 150 MSPS Wideband Digital Down-Converter (DDC)
AD6636PCB 150 MSPS Wideband Digital Down-Converter (DDC)
AD664(中文) Monolithic 12-Bit Quad DAC(單片12位四D/A轉(zhuǎn)換器)
AD6640 12-Bit, 65 MSPS IF Sampling A/D Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6636BC 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC)
AD6636BC/PCB 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk
AD6636BC/PCBZ 制造商:Analog Devices 功能描述:Evaluation Kit For 150 MSPS, Wide Band, Digital Down Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk
AD6636CBC 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD6636CBCZ 功能描述:IC DIGITAL DWNCONV 4CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3）
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*