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參數(shù)資料
| 型號(hào)： | AD6636BBCZ1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁(yè)數(shù)： | 57/72頁(yè) |
| 文件大小： | 1629K |
| 代理商： | AD6636BBCZ1 |
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AD6636
<4>: Channel 4 Access Bit. Similar to Bit <5> for Channel 4.
Rev. 0 | Page 57 of 72
<3>: Channel 3 Access Bit. Similar to Bit <5> for Channel 3.
<2>: Channel 2 Access Bit. Similar to Bit <5> for Channel 2.
<1>: Channel 1 Access Bit. Similar to Bit <5> for Channel 1.
<0>: Channel 0 Access Bit. Similar to Bit <5> for Channel 0.
Note: If the access bits are set for more than one channel, during
write access all channels with access are written with same the
data. This is especially useful when more than one channel has
similar configurations. During a read operation, if more than
one channel has access, the read access is given to the channel
with the lowest channel number. For example, if both Channel 4
and Channel 2 have access bits set, then read access is given to
Channel 2.
Channel Enable Register <5:0>
<5>: Channel 5 Enable Bit. When this bit is set, Channel 5 logic
is enabled. When this bit is cleared, Channel 5 is disabled and
the channel’s logic does not consume any power. On power-up,
this bit comes up with Logic 0 and the channel is disabled. A
start sync does not start Channel 5 unless this bit is set before
issuing the start sync.
<4>: Channel 4 Enable Bit. Similar to Bit <5> for Channel 4.
<3>: Channel 3 Enable Bit. Similar to Bit <5> for Channel 3.
<2>: Channel 2 Enable Bit. Similar to Bit <5> for Channel 2.
<1>: Channel 1 Enable Bit. Similar to Bit <5> for Channel 1.
<0>: Channel 0 Enable Bit. Similar to Bit <5> for Channel 0.
Pin Synchronization Configuration <7:0>
<7>: Hop Synchronization Enable Bit. This bit is a global enable
for any hop synchronization involving SYNC pins. When this
bit is set, hop synchronization is enabled for all channels that
are programmed for pin synchronization. When this bit is
cleared, hop synchronization is not performed for any channel
that is programmed for pin synchronization.
<6>: Start Synchronization Enable Bit. This bit is a global enable
for any start synchronization involving SYNC pins. When this
bit is set, start synchronization is enabled for all channels that
are programmed for pin synchronization. When this bit is
cleared, start synchronization is not performed for any channel
that is programmed for pin synchronization.
<5>: First Sync Only Bit. When this bit is set, the NCO
synchronization logic recognizes only the first synchronization
event as valid. All other requests for synchronization events are
ignored as long as this bit is set. When cleared, all synchro-
nization events are acted upon.
<4>: Edge-Sensitivity Bit. When this bit is set, the rising edge on
the SYNC pin(s) is detected as a synchronization event (edge-
sensitive detection). When cleared, Logic 1 on the SYNC pin(s)
is detected as a synchronization event (level-sensitive
detection).
<3>: Enable Synchronization from SYNC3 Bit. When this bit is
set, the SYNC3 pin can be used for synchronization. When this
bit is cleared, the SYNC3 pin is ignored. This is a global enable
for all SYNC pins, and each individual channel selects which
pin it listens to.
<2>: Enable Synchronization from SYNC2 Bit. Similar to
Bit <3> for the SYNC[2] pin.
<1>: Enable Synchronization from SYNC1 Bit. Similar to
Bit <3> for the SYNC1 pin.
<0>: Enable Synchronization from SYNC0 bit. Similar to
Bit <3> for the SYNC0 pin.
Soft Synchronization Configuration <7:0>
<7>: Soft Hop Synchronization Enable Bit. When this bit is set,
hop synchronization is enabled for all channels selected using
Bits 5:0. When this bit is cleared, hop synchronization is not
performed for any channels selected using Bits 5:0.
<6>: Soft Start Synchronization Enable Bit. When this bit is set,
start synchronization is enabled for all channels selected using
Bits 5:0. When this bit is cleared, start synchronization is not
performed for any channels selected using Bits 5:0.
Bits<5:0> form the SOFT_SYNC control bits. These bits can be
written to by the controller to initiate the synchronization of a
selected channel.
<5>: Soft Sync Channel 5 Enable Bit. When this bit is set, it
enables Channel 5 to receive a hop sync or start sync, as defined
by Bits 7 and 6, respectively. When cleared, Channel 5 does not
receive any soft sync.
<4>: Soft Sync Channel 4 Enable Bit. Similar to Bit <5> for
Channel 4.
<3>: Soft Sync Channel 3 Enable Bit. Similar to Bit <5> for
Channel 3.
<2>: Soft Sync Channel 2 Enable Bit. Similar to Bit <5> for
Channel 2.
<1>: Soft Sync Channel 1 Enable Bit. Similar to Bit <5> for
Channel 1.
<0>: Soft Sync Channel 0 Enable Bit. Similar to Bit <5> for
Channel 0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD6636BC | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636BC/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 150 MSPS, Wide Band, Digital Down Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636CBC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD6636CBCZ | 功能描述:IC DIGITAL DWNCONV 4CH 256CSPBGA RoHS:是 類(lèi)別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤(pán) 封裝/外殼:12-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
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