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參數(shù)資料
| 型號： | AD6636BBCZ1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁數(shù)： | 62/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636BBCZ1 |
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AD6636
<0>: Gain Control Enable Bit. This bit controls the configura-
tion of the EXP<2:0> bits for Channel A. When the gain control
enable bit is Logic 1, the EXP<2:0> bits are configured as
outputs. When this bit is cleared, the EXP<2:0> bits are inputs.
Port A Dwell Timer <19:0>
This register is used to set the dwell time for the gain control
block. When gain control block is active and detects a decrease
in the signal level below the lower threshold value (program-
mable), a dwell time counter is initiated to provide temporal
hysteresis. Doing so prevents the gain from being switched
continuously. Note that the dwell timer is turned on only after a
drop below the lower threshold is detected in the signal level.
Port A Power Monitor Period <23:0>
This register is used in the power monitoring logic to set the
period of time for which ADC input data is monitored. This
value represents the monitor period in number of ADC port
clock cycles.
Port A Power Monitor Output <23:0>
This register is read-only and contains the current status of the
power monitoring logic output. The output is dependent on the
power monitoring mode selected. When the power monitor
block is enabled, this register is updated at the end of each
power monitor period. This register is updated even if an
interrupt signal is not generated.
Port A Upper Threshold <9:0>
This register serves the dual purpose of specifying the upper
threshold value in the gain control block and in the power
monitoring block, depending on which block is active. Any
ADC port input data having a magnitude greater than this value
triggers a gain change in the gain control block. Any ADC port
input data having a magnitude greater than this value is
monitored in the power monitoring block (in peak detect or
threshold crossing mode). The value of the register is compared
with the absolute magnitude of the input port data. For real
input, the absolute magnitude is the same as the input data; for
positive and negative data, the absolute magnitude is the value
of the data after removing the negative sign.
Port A Lower Threshold <9:0>
This register is used in the gain control block and represents the
magnitude of the lower threshold for ADC port input data. Any
ADC input data having a magnitude below the lower threshold
initiates the dwell time counter. The value of the register is
compared with the absolute magnitude of the input port data.
Rev. 0 | Page 62 of 72
For real input, the absolute magnitude is the same as the input
data; for positive and negative data, the absolute magnitude is
the value of the data after removing the negative sign.
Port A Signal Monitor <4:0>
This register controls the functions of the power monitoring
block.
<4>: Disable Power Monitor Period Timer Bit. When this bit is
set, the power monitor period timer no longer controls the
update of the power monitor holding register. A user read to the
power monitor holding register updates this register. When this
bit is cleared, the power monitor period register controls the
timer and, therefore, controls the update rate of the power
monitor holding register.
<3>: Clear-on-Read Bit. When this bit is set, the power monitor
holding register is cleared every time this register is read. This
bit controls whether the power monitoring function is cleared
after a read of the power monitor period register. If this bit is
set, the monitoring function is cleared after the read. If this bit is
Logic 0, the monitoring function is not cleared. This bit is a
don’t care if the disable integration counter bit is clear.
<2:1>: Monitor Function Select Bits. Table 33 lists the functions
of these bits.
Table 33. Monitor Function Select Bits
Monitor Function Select
00
01
10
11
Function Enabled
Peak Detect Mode
Mean Power Monitor Mode
Threshold Crossing Mode
Invalid Selection
<0>: Monitor Enable Bit. When this bit is set, the power
monitoring function is enabled and operates as selected by
Bits <2:1> of the signal monitor register. When this bit is
cleared, the power monitoring function is disabled and the
signal monitor register <2:1> bits are don’t care. This bit defaults
to 0 on power-up.
Note: Gain control, dwell timer, power monitor period, signal
monitor, power monitoring output, lower threshold and upper
threshold registers for Ports B, C, and D work similarly to the
corresponding registers definitions for Port A.
CHANNEL REGISTER MAP
Channel control registers are common to all six channels, and
access to specific channels is determined by the channel I/O
access register (Address 0x02).
NCO Control <15:0>
These bits control the NCO operation.
<8:7>: NCO Sync Start Select Bits. These bits determine which
SYNC input pin is used by this channel for a start synchroniza-
tion operation. Table 34 describes the selection.
Table 34. Sync Start Select Bits
NCO Control <8:7>
00
01
10
11
SYNC Pin Used for Start Synchronization
SYNC0
SYNC1
SYNC2
SYNC3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6636BC | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636BC/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 150 MSPS, Wide Band, Digital Down Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636CBC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD6636CBCZ | 功能描述:IC DIGITAL DWNCONV 4CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
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