參數(shù)資料
型號： AD6654CBCZ
廠商： Analog Devices Inc
文件頁數(shù)： 13/88頁
文件大小： 0K
描述： IC ADC 14BIT W/4CH RSP 256CSPBGA
標準包裝： 1
位數(shù)： 14
采樣率（每秒）： 92.16M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 2.5W
電壓電源： 模擬和數(shù)字
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA，CSPBGA
供應商設備封裝： 256-CSPBGA（17x17）
包裝： 托盤
輸入數(shù)目和類型： 1 個差分，單極
AD6654
Rev. 0 | Page 20 of 88
Name
Type
Pin Number
Function
DDC INPUTS
CLK
Input
A11
DDC Clock Input.
SYNC0
Input
T10
Synchronization Input 0. SYNC pins are independent of channels.
SYNC1
Input
R11
Synchronization Input 1.
SYNC2
Input
P11
Synchronization Input 2.
SYNC3
Input
T11
Synchronization Input 3.
DDC OUTPUTS
EXPC [2:0]
Output
D11, C11, B11
External VGA Gain Control Bits. GND all pins if not used.
DDC OUTPUT PORTS
PCLK
Bi-dir
T4
Parallel Output Port Clock. PCLK is bi-directional: master mode = output, slave mode = input.
PADATA[15:0]
Output
See
Parallel Output Port A Data Bus.
PACH[2:0]
Output
D8, R5, C8
Channel Indicator Output Port A.
PAIQ
Output
A8
Parallel Port A I/Q Data Indicator. Logic 1 indicates I data on data bus.
PAGAIN
Output
A9
Parallel Port A Gain Word Output Indicator. Logic 1 indicates gain word on data bus.
PAACK
Input
B8
Parallel Port A Acknowledge (Active High).
PAREQ
Output
N6
Parallel Port A Request (Active High).
PBDATA[15:0]
Output
See
Parallel Output Port B Data Bus.
PBCH[2:0]
Output
P10, P8, R8
Channel Indicator Output Port B.
PBIQ
Output
T7
Parallel Port B I/Q Data Indicator. Logic 1 indicates I data on data bus.
PBGAIN
Output
R10
Parallel Port B Gain Word Output Indicator. Logic 1 indicates gain word on data bus.
PBACK
Input
P9
Parallel Port B Acknowledge (Active High).
PBREQ
Output
N8
Parallel Port B Request (Active High)
PCDATA[15:0]
Output
See
Parallel Output Port C Data Bus.
PCCH[2:0]
Output
M5, A6, R1
Channel Indicator Output Port C.
PCIQ
Output
P1
Parallel Port C I/Q Data Indicator. Logic 1 indicates I data on data bus.
PCGAIN
Output
R2
Parallel Port C Gain word Output Indicator. Logic 1 indicates gain word on data bus.
PCACK
Input
E5
Parallel Port C Acknowledge (Active High).
PCREQ
Output
P2
Parallel Port C Request (Active High).
MICROPORT CONTROL
D[15:0]
Bi-Dir
See
Bidirectional Microport Data. This bus is three-stated when CS is high.
A[7:0]
Input
See
Microport Address Bus.
DS (RD)
Input
B4
Active Low Data Strobe, MODE = 1. Active low read strobe when MODE = 0.
DTACK (RDY)1
Output
C3
Active Low Data Acknowledge, MODE = 1. Microport status pin when MODE = 0. Terminate
to VDDIO through external 1 k pull-up resistor.
R/W (WR)
Input
C4
Read/Write Strobe, MODE = 1. Active low write strobe when MODE = 0.
MODE
Input
C2
Mode Select. Logic 0 = Intel mode, Logic 1 = Motorola mode.
CS
Input
D3
Active Low Chip Select. Logic 1 three-states the microport data bus.
CPUCLK
Input
A4
Microport CLK Input. (Input only.)
CHIPID[3:0]
Input
C1, E1, B3, B2
Chip ID Input Pins.
SERIAL PORT CONTROL
SCLK
Input
A4
Serial Clock. Should have a rise/fall time of 3ns max.
Output
C3
Serial Port Data Output. Terminate to VDDIO through external 1 k pull-up resistor.
Input
K3
Serial Port Data Input.
STFS
Input
C4
Serial Transmit Frame Sync.
SRFS
Input
B4
Serial Receive Frame Sync.
SCS
Input
D3
Serial Chip Select.
MSB_FIRST
Input
D2
Most Significant Bit_First. Selects MSB_FIRST into SDI pin, and MSB_FIRST out of SDO pin.
Logic 1 = MSB_FIRST; Logic 0 = LSB_FIRST
SMODE
Input
F1
Serial Mode Select.
MISC PINS
DNC
-------
B12, T9
Do Not Connect.
Output
E2
Interrupt Pin (Active Low). Terminate to VDDIO through external 1 k pull-up resistor.
RESET
Input
F4
Master Reset, Active Low.
EXT_FILTER
Input
D1
PLL Loop Filter (Analog Pin). Connect to VDDCORE through series 250 and 0.01 F
capacitor.
1 Pins with internal pull-up resistor of nominal 70 k.
2 Pins with internal pull-down resistor of nominal 70 k.
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