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參數(shù)資料
| 型號： | AD6654CBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 50/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT W/4CH RSP 256CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 92.16M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSPBGA（17x17） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
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AD6654
Rev. 0 | Page 54 of 88
PCLK
tDPREQ
PxREQ
PxACK
tDPP
Px [15:0]
I[15:0]
Q[15:0]
PxIQ
tDPIQ
PxCH [2:0]
PxCH [2:0] = CHANNEL #
tDPCH
0000 +
GAIN [11:0]
PxGAIN
tDPGAIN
05156-047
Figure 58. Interleaved I/Q Mode with an AGC Gain Word
PxCH [2:0]
PCLK
tDPREQ
PxREQ
PxACK
tDPP
Px [15:0]
I [15:8]
Q [15:8]
PxIQ
tDPIQ
PxCH [2:0] =
AGC NO.
tDPCH
PxGAIN
LOGIC LOW 0
05156-048
Figure 59. Parallel I/Q Mode Without an AGC Gain Word
When an output data sample is available for output from an
AGC, the parallel port initiates the transfer by pulling the
PxREQ signal high. In response, the processor receiving the
data needs to pull the PxACK signal high, acknowledging that it
is ready to receive the signal. In Figure 59, the PxACK is already
pulled high and, therefore, the 8-bit I data and 8-bit Q data are
simultaneously output on the data bus on the next PCLK rising
edge after PxREQ is driven logic high. The PxIQ signal also
goes high to indicate that I/Q data is available on the data bus.
When I/Q data is being output, the channel indicator pins
PxCH[2:0] indicate the data source (AGC number).
Figure 59 is the timing diagram for parallel I/Q mode with the
AGC gain word disabled. Figure 60 is a similar timing diagram
with the AGC gain word enabled. In the PCLK cycle after the
I/Q data, the AGC gain word is output on the data bus, and the
PxGAIN signal is pulled high to indicate that the gain word is
available on the parallel port. During this PCLK cycle, the PxIQ
signal is pulled low to indicate that I/Q data is not available on
the data bus. Therefore, in parallel I/Q mode, a minimum of
two PCLK cycles is required to output one sample of output
data on the parallel port without and with the AGC gain word,
respectively.
The order of data output is dependent on when data arrives at
the port, which is a function of total decimation rate, DRCF/
CRCF decimation phase, and start hold-off values. Priority
order from highest to lowest is, AGC0, AGC1, AGC2, AGC3,
AGC4, and AGC5 for both parallel I/Q and interleaved modes
of output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-125EBZ | 功能描述:BOARD EVAL W/AD6655 & SOFTWARE RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
| AD6655-125EBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-150EBZ | 功能描述:BOARD EVAL FOR 150MSPS AD6655 RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
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