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參數(shù)資料
| 型號(hào)： | AD6654CBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT W/4CH RSP 256CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 92.16M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSPBGA（17x17） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
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AD6654
Rev. 0 | Page 29 of 88
05156-030
BALANCE
50
SOURCE
25
100nF
25
100nF
AD8351
INHI
INLO
RG
OPHI
OPLO
VOCM
25
25
DIGITAL
OUT
AD6654
AIN+
AIN–
VREF
100nF
Figure 40. ADC Driving Application Using Differential Input
05156-062
SINGLE-
ENDED
50
SOURCE
R1
25
100nF
25
100nF
AD8351
INHI
INLO
RG
OPHI
OPLO
VOCM
25
25
DIGITAL
OUT
AD6654
AIN+
AIN–
VREF
100nF
RF
Figure 41. ADC Driving Application Using Single-Ended Input
DDC CONFIGURATION NOTES
PLL Clock Multiplier
In the AD6654, the input clock rate must be the same as the
input data rate. In a typical digital down-converter architecture,
the clock rate is a limitation on the number of filter taps that
can be calculated in the programmable RAM coefficient filters
(MRCF, DRCF, and CRCF). For slower ADC clock rates (or for
any clock rate), this limitation can be overcome by using a PLL
clock multiplier to provide a higher clock rate to the RCF filters.
Using this clock multiplier, the internal signal processing clock
rate can be increased up to 200 MHz. The CLK signal is used as
an input to the PLL clock multiplier.
05156-031
CLK
PLL_CLK
ADC_CLK
DIVIDE BY N
(1, 2, 4 OR 8)
PLL CLOCK
MULTIPLIER
(4x TO 20x)
PLL CLOCK GENERATION
BYPASS_PLL
1 FOR BYPASS
NM
2
5
0
1
0
Figure 42. PLL Clock Generation
The PLL clock multiplier is programmable and uses the input
clock rates between 30 MHz and 92.16 MHz to give a system
clock rate (output) of as high as 200 MHz.
The output clock rate is given by
N
M
CLK
PLL
×
=
_
where:
CLK
is the input port clock rate.
M
is a 5-bit programmable multiplication factor.
N
is a predivide factor and can be 1, 2, 4, or 8.
M
is a 5-bit number between 4 and 20 (inclusive).
The multiplication factor, M, is programmed using a 5-bit PLL
clock multiplier word in the ADC clock control register. A value
outside the valid range of 4 to 20 bypasses the PLL clock
multiplier and, therefore, the PLL clock is the same as the input
clock. The predivide factor, N, is programmed using a 2-bit
ADC pre-PLL clock divider word in the ADC clock control
register, as listed in Table 13.
Table 13. PLL Clock Generation Predivider Control
Predivide Word [1:0]
Divide-By Value for the Clock
00
Divide-by-1, bypass
01
Divide-by-2
10
Divide-by-4
11
Divide-by-8
For best signal processing advantage, the user should program
the clock multiplier to give a system clock output as close as
possible to, but not exceeding, 200 MHz. The internal blocks of
the AD6654 that run off the PLL clock are rated to run at a
maximum of 200 MHz. The default power-up state for the PLL
clock multiplier is the bypass state, where CLK is passed on as
the PLL clock.
ADC Gain Control
The DDC input port has individual, high speed gain control
logic circuitry. Such gain control circuitry is useful in applica-
tions that involve large dynamic-range inputs. The AD6654 gain
control logic allows programmable upper and lower thresholds
and a programmable dwell-time counter for temporal
hysteresis.
The DDC input port has a 3-bit output from the gain control
block. The operation is controlled by the gain control enable bit
in the gain control register of the DDC input port. Logic 1 in
this bit programs the EXP[2:0] pins as gain control outputs.
Function
The gain control block features a programmable upper thresh-
old register and a lower threshold register. The ADC input data
is compared to both these registers. If ADC input data is larger
than the upper threshold register, then the gain control output
is decremented by 1. If the ADC input data is smaller than the
lower threshold register, then the gain control output is incre-
mented by 1.
When decrementing the gain control output, the change is
immediate. But when incrementing the output, a dwell-time
register is used to delay the change. If the ADC input is larger
than the upper threshold register value, the gain control output
is immediately decremented to prevent overflow.
When the ADC input is lower than the lower threshold register,
a dwell timer is loaded with the value in the programmable
20-bit dwell-time register. The counter decrements once every
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-125EBZ | 功能描述:BOARD EVAL W/AD6655 & SOFTWARE RoHS:是 類別:RF/IF 和 RFID >> RF 評(píng)估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
| AD6655-125EBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-150EBZ | 功能描述:BOARD EVAL FOR 150MSPS AD6655 RoHS:是 類別:RF/IF 和 RFID >> RF 評(píng)估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
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